GAA Nanosheet Transistor Structure With Expanded Source/Drain Contact
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Solution Overview
Problem
Existing nanostructure transistors have limited contact area between the source/drain structure and channel layers, which impedes performance improvement.
Innovation Solution
The formation of a gate-all-around (GAA) field-effect-transistor (FET) device with increased contact area between the source/drain structure and channel layers by contacting the source/drain structure through the sidewall, top surface, and bottom surface of each channel layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar transistor structures are used, then manufacturing is simpler, but integration density and performance are limited
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanosheet channel structures with gate-all-around configuration. The channel layers are arranged vertically in multiple stacks, and the gate structure wraps around the channel from all directions (top, bottom, and sidewalls), creating a 3D configuration that increases effective channel width and integration density while maintaining manufacturability through established semiconductor fabrication processes
2Reliability
If source/drain structure contacts only sidewall of channel layers, then manufacturing is easier, but contact area is limited and performance is impaired
Solution Approach 1:
The contact structure evolves from 1D sidewall-only contact to multi-dimensional contact by forming source/drain structures that contact the channel layers through sidewalls, top surfaces, and bottom surfaces. This is achieved by recessing the channel layers at angled orientations and forming source/drain structures that extend into these recesses, creating extensive contact interfaces that improve electrical connection and transistor performance
3Productivity
If minimum feature size is continuously reduced, then integration density improves, but manufacturing precision requirements increase
Solution Approach 1:
The patent divides the channel structure into multiple discrete nanosheet layers stacked vertically, with each layer separated by insulating materials. This segmentation allows each layer to be formed and controlled independently through selective epitaxial growth, enabling precise thickness control of individual layers while achieving high overall integration density. The segmented structure also facilitates better stress control and electrical isolation between channels
Data Source
AI summary
A semiconductor device includes a plurality of channel layers vertically spaced from one another, a gate structure wrapping around each of the plurality of channel layers; and an inner spacer that is disposed along sidewalls of a lower portion of the gate structure. The inner spacer curves toward the lower portion of the gate structure.