GAA Nanosheet Etching for Uniform Inner Spacer Profiles
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Solution Overview
Problem
The semiconductor industry faces challenges in achieving precise control over the profiles of nanosheets and inner spacers in gate all around (GAA) transistor structures, which affects the electrical mobility and quality of the gate structure, particularly due to issues with oxygen impurities and native oxides in the semiconductor layers.
Innovation Solution
A method involving hydrogen radical treatment and selective chemical dry etching processes is employed to remove oxygen impurities and recess the first semiconductor layers, forming inner spacers with uniform profiles and improving the surface roughness of the second semiconductor layers, allowing for better epitaxial growth and electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used to form nanosheets and inner spacers, then manufacturing is simpler, but profile control precision deteriorates
Solution Approach 1:
The method performs preliminary actions by forming dummy gate structures and sacrificial layers before the final gate structure is created. These preliminary structures enable precise profile control of nanosheets and inner spacers through selective etching and recess processes, which would be difficult to achieve with conventional direct fabrication methods.
Solution Approach 2:
The fabrication process is segmented into multiple distinct stages: forming stacked semiconductor layers, creating dummy gate structures, selective removal of sacrificial layers, forming inner spacers, and final gate structure creation. This segmentation allows each step to be optimized independently for profile control precision.
2Reliability
If oxygen impurities and native oxides are present in semiconductor layers, then manufacturing is easier, but electrical mobility deteriorates
Solution Approach 1:
The method extracts and removes oxygen impurities and native oxides from the semiconductor layers through selective etching processes. By targeting and removing these harmful substances from the crystal structure, the patent improves electrical mobility without requiring complete redesign of the fabrication process.
Solution Approach 2:
The patent changes chemical parameters by introducing specific etchants and controlling etching conditions to selectively remove oxygen-containing compounds. This parameter change enables differentiation between desired semiconductor material and harmful oxygen impurities, achieving high electrical mobility while maintaining manufacturing feasibility.
3Manufacturing precision
If inner spacers are formed without precise profile control, then manufacturing is simpler, but gate structure quality deteriorates
Solution Approach 1:
The dummy gate structures serve as preliminary templates that define the precise profile of inner spacers. By establishing this template structure beforehand, the method ensures uniform spacer profiles during mass production without requiring complex real-time control mechanisms.
Solution Approach 2:
The self-aligned nature of the process allows structures to automatically define their own positions and profiles. The dummy gates and sacrificial layers self-organize to create uniformly spaced inner spacers, reducing the need for additional alignment steps and maintaining productivity during mass production.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the electrical mobility and quality of the gate structure by removing oxygen impurities and achieving uniform spacer profiles, thereby improving the performance of GAA transistors and facilitating mass production.
Implementation Method 1
a hydrogen radical treatment is performed on the remaining first and second semiconductor layers to remove oxygen in the first and second semiconductor layers
Implementation Method 2
a selective chemical dry etching process is then performed using a fluorine-containing gas to laterally recess the first semiconductor layers in the first portion of the fin structure
Data Source
AI summary
A method includes forming a fin structure including a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over a substrate. A dummy gate structure is formed across the fin structure. The exposed second portions of the fin structure are removed. A selective etching process is performed, using a gas mixture including a hydrogen-containing gas and a fluorine-containing gas, to laterally recess the first semiconductor layers. Inner spacers are formed on opposite end surfaces of the laterally recessed first semiconductor layers. Source/drain epitaxial structures are formed on opposite end surfaces of the second semiconductor layers. The dummy gate structure is removed to expose the first portion of the fin structure. The laterally recessed first semiconductor layers are removed. A gate structure is formed to surround each of the second semiconductor layers.