GAA Nanosheet Transistor Layout for Dense FeRAM Integration
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Solution Overview
Problem
The increasing memory cell density in semiconductor memory devices leads to compact structure designs with reduced sizes, posing challenges in maintaining performance.
Innovation Solution
Integration of gate all-around (GAA) transistor structures with ferroelectric random access memory (FeRAM) devices, utilizing multi-patterning photolithography processes to create smaller pitches and enhance memory device integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell density is increased to enhance integration density, then device size is reduced, but manufacturing precision and structural complexity become more challenging to maintain
Solution Approach 1:
The transistor structure is segmented into multiple semiconductor layers (first semiconductor layer, second semiconductor layer, third semiconductor layer) stacked vertically, with each layer serving specific functional purposes. This segmentation allows the device to achieve high integration density while maintaining manufacturable dimensions and precision requirements for each individual layer.
Solution Approach 2:
The patent transitions from planar transistor structures to three-dimensional stacked structures by arranging semiconductor layers vertically in the z-direction. This dimensional change enables higher memory cell density without proportionally increasing manufacturing precision requirements in the lateral dimensions, as the stacking provides additional integration capacity through the vertical dimension.
2Quantity of substance
If device size is reduced to increase integration density, then more devices can be integrated, but electrical connectivity and performance maintenance become more difficult
Solution Approach 1:
The gate electrode is designed to wrap around and surround the stacked semiconductor layers and source/drain regions, creating a nested configuration where the gate envelops the active regions. This all-around gate structure provides comprehensive electrical control and connectivity over the stacked channels, ensuring reliable performance despite the reduced device footprint and increased integration density.
Solution Approach 2:
The gate electrode adopts a curved, wraparound geometry that envelops the semiconductor layers from multiple directions, providing uniform electrical field distribution and consistent control over the stacked channels. This curved configuration enhances electrical connectivity and control effectiveness compared to planar gate structures, maintaining reliability at scaled dimensions.
3Quantity of substance
If multi-patterning photolithography is used to create smaller pitches, then integration density increases, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The semiconductor structure is divided into multiple discrete layers formed through separate deposition and patterning steps. Each semiconductor layer can be independently fabricated and positioned, allowing the use of multi-patterning photolithography on individual layers without compounding the complexity across the entire structure. This layer-by-layer segmentation makes the complex manufacturing process more manageable.
Solution Approach 2:
Semiconductor layers are deposited and patterned in advance before final assembly and stacking. The multi-patterning photolithography processes are performed on individual layers during these preliminary fabrication steps, establishing the precise pitch requirements before the layers are combined. This preliminary patterning reduces the overall manufacturing complexity by breaking down the complex task into simpler, sequential operations.
Data Source
AI summary
A transistor includes a first semiconductor layer, a second semiconductor layer, a semiconductor nanosheet, a gate electrode and source and drain electrodes. The semiconductor nanosheet is physically connected to the first semiconductor layer and the second semiconductor layer. The gate electrode wraps around the semiconductor nanosheet. The source and drain electrodes are disposed at opposite sides of the gate electrode. The first semiconductor layer surrounds the source electrode, the second semiconductor layer surrounds the drain electrode, and the semiconductor nanosheet is disposed between the source and drain electrodes.