GAA Nanosheet Fin Layout for Lower Gate-to-Contact Capacitance
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Solution Overview
Problem
The increasing complexity of semiconductor manufacturing due to scaling down processes leads to challenges in reducing coupling capacitance between gate structures and adjacent source/drain contact features, particularly exacerbated by Shallow Trench Isolation (STI) oxide loss.
Innovation Solution
A back-side gate etch back process is employed to etch away excess material of the gate structure, reducing coupling capacitance by etching from the substrate side, and utilizing double-patterning or multi-patterning techniques to form gate all around (GAA) transistor structures with nanostructures wrapped by a gate dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If scaling down process is used to increase functional density, then production efficiency is improved and costs are lowered, but manufacturing complexity increases and coupling capacitance between gate structures and source/drain contacts increases
Solution Approach 1:
The fabrication process is divided into multiple sequential patterning steps (double-patterning or multi-patterning techniques) to form the gate structure. This segmentation allows precise control over the gate dimensions and positioning, enabling scaling down while managing the increased manufacturing complexity through systematic process breakdown.
Solution Approach 2:
The gate structure is formed to extend around adjacent source/drain contact features in three dimensions, creating an enveloping configuration. This dimensional approach allows the gate to be positioned such that its bottom surface is coplanar with the top surface of isolation structures, effectively reducing coupling capacitance while maintaining scaled-down dimensions.
2Area of moving object
If gate structure dimensions are reduced to increase functional density, then more devices fit per chip area, but coupling capacitance between gate and source/drain contacts increases
Solution Approach 1:
The gate structure is configured to extend around adjacent source/drain contact features in three dimensions, with the bottom surface of the gate coplanar with the top surface of isolation structures. This spatial arrangement reduces the coupling capacitance between the gate and source/drain contacts while maintaining reduced gate dimensions for high functional density.
Solution Approach 2:
Isolation structures are introduced as intermediary elements between the gate structure and source/drain contact features. These isolation structures provide physical separation and electrical isolation, reducing the harmful coupling capacitance effect while allowing the gate to maintain its reduced dimensions for high density integration.
3Ease of manufacture
If conventional fabrication processes are used, then manufacturing is simpler, but coupling capacitance cannot be effectively reduced
Solution Approach 1:
The fabrication process is segmented into multiple patterning steps that systematically form the gate structure with precise dimensional control. This segmented approach, while more complex than conventional single-step processes, enables the gate bottom surface to be coplanar with isolation structure tops, effectively reducing coupling capacitance.
Solution Approach 2:
Isolation structures are formed in advance before the gate structure is created. This preliminary action establishes the reference plane (top surface of isolation structures) against which the gate bottom surface is made coplanar, enabling effective coupling capacitance reduction while maintaining a systematic fabrication flow.
Data Source
AI summary
A semiconductor device includes a plurality of stacks that each includes a plurality of nanostructures stacked over each other, a gate structure wrapping around the nanostructures and extending between the stacks, source and drain structures, and a plurality of fin structures respectively disposed on the stacks. A first surface of the gate structure between the stacks is substantially coplanar with first surfaces of the fin structures facing to the nanostructures or between the first surfaces of the fin structures and the nanostructures.