GAA Nanosheet Gate Formation Without Fluorine Precursors
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Solution Overview
Problem
The challenge in fabricating horizontal gate-all-around (HGAA) transistors is the unsatisfactory nanosheet formation using current methods, particularly with a single epitaxial process, which leads to compromised gate control and increased short-channel effects due to scaling down of transistor gate lengths.
Innovation Solution
A method involving sequential processes such as impurity ion implantation, formation of stacked semiconductor layers, patterning, and selective etching to create fin structures, followed by the formation of a metal gate structure around suspended semiconductor nanosheets, using fluorine-free precursors to improve threshold voltage stability and control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If gate lengths are scaled down to increase drive current, then transistor performance is improved, but short-channel effects increase and gate control is compromised
Solution Approach 1:
The patent transitions from planar gate structures to three-dimensional gate-all-around structures that wrap around the channel region. This dimensional change provides gate control from multiple directions (top, bottom, and sides), significantly enhancing electrostatic control over the channel and reducing short-channel effects while maintaining scaled-down gate lengths for high drive current.
Solution Approach 2:
The gate structure is nested around the channel region, with the gate wrapping completely around the channel in a gate-all-around configuration. This nested arrangement ensures that the gate electrode surrounds the channel from multiple directions, providing superior control over carrier flow and mitigating short-channel effects.
2Ease of manufacture
If single epitaxial process is used for nanosheet formation, then manufacturing simplicity is maintained, but nanosheet formation quality is unsatisfactory
Solution Approach 1:
The patent divides the nanosheet formation process into multiple sequential steps, including separate epitaxial growth stages and selective removal processes. This segmentation allows each step to be optimized independently, achieving high-quality nanosheet formation with precise thickness control and uniformity while maintaining compatibility with existing manufacturing processes.
Solution Approach 2:
The methodology employs preliminary actions such as forming sacrificial layers and using selective epitaxial growth before final nanosheet release. These preliminary steps prepare the structure in advance, enabling precise nanosheet formation and ensuring high manufacturing quality through controlled material deposition and removal sequences.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the fabrication of gate-all-around transistors by improving nanosheet formation, reducing short-channel effects, and stabilizing the threshold voltage, thereby addressing the limitations of current methods in scaling down transistor performance.
Implementation Method 1
impurity ion implantation
Implementation Method 2
formation of stacked semiconductor layers
Data Source
AI summary
A method of forming a semiconductor device including forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, etching the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a work function metal layer surrounding each of the nanosheets, and depositing a fill metal layer over the work function metal layer without using a fluorine-containing precursor.