Gate-All-Around Nanosheet Sidewall Treatment for Uniform Gate Length
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Solution Overview
Problem
The integration of multi-gate devices, such as nanowire and nanosheet transistors, on integrated circuits faces challenges due to lateral etch rate differences causing non-uniform sidewall surfaces and vertical profile distortions, leading to inconsistent gate length patterning.
Innovation Solution
A method involving the lateral etching of alternating first and second layers of nanosheets to create uniform sidewalls, followed by forming an inner spacer over the recessed second layers, and performing a sidewall treatment to enhance uniformity, which is facilitated by a system comprising a processor and memory for executing these processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If lateral etching is performed on nanosheets to create multi-gate devices, then gate control is improved, but sidewall uniformity deteriorates due to etch rate differences
Solution Approach 1:
The nanosheet stack is segmented into alternating first and second layers with different etch rates. By selectively etching the second layers laterally relative to the first layers, the patent creates a segmented structure where each layer type can be processed differently, enabling improved gate control while managing sidewall uniformity through controlled differentiation.
Solution Approach 2:
The patent applies local quality by creating different etch characteristics at different locations within the nanosheet stack. The second layers are locally modified to have different etch rates compared to the first layers, allowing targeted lateral recessing in specific regions while maintaining overall structural integrity and controlled sidewall profiles.
2Ease of manufacture
If conformal spacers are formed over non-uniform sidewalls, then gate length patterning is achieved, but gate length consistency deteriorates due to profile distortion
Solution Approach 1:
The patent performs preliminary selective lateral etching of the second layers before forming the conformal spacers. This preliminary action creates a pre-conditioned sidewall profile where the alternating layer structure compensates for potential distortions, ensuring that when spacers are subsequently formed, they inherit a more uniform underlying geometry that leads to consistent gate length patterning.
Solution Approach 2:
The patent changes the etch rate parameter selectively for different layers by using materials with different etch characteristics (first layers vs. second layers). This parameter differentiation allows the creation of a compensated sidewall profile that maintains uniformity despite the multi-step processing, enabling consistent gate length when spacers are formed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces dummy gate CD variation and improves nanosheet gate length uniformity, enabling the formation of optimized gate-all-around transistors with consistent gate lengths.
Implementation Method 1
etching the plurality of nanosheets to laterally recess the second layers relative to the first layers
Implementation Method 2
forming a spacer material along an exposed portion of each of the plurality of nanosheets
Implementation Method 3
etching the spacer material to remove the spacer material from the first layers of each of the plurality of nanosheets
Data Source
AI summary
Approaches herein provide devices and methods for forming optimized gate-all-around transistors. One method may include forming a plurality of nanosheets each comprising a plurality of alternating first layers and second layers, and etching the plurality of nanosheets to laterally recess the second layers relative to the first layers. The method may further include forming an inner spacer over the recessed second layers by forming a spacer material along an exposed portion of each of the plurality of nanosheets, etching the spacer material to remove the spacer material from the first layers of each of the plurality of nanosheets, and performing a sidewall treatment to the plurality of nanosheets after the spacer material is removed from the first layers of each of the plurality of nanosheets.