GAA Nanosheet FETs With Region-Specific Gate Oxide Thickness
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Solution Overview
Problem
Existing multiple gate field-effect transistors face challenges in continuously scaling down gate stacks for input/output (I/O) and core devices with different gate oxide layer thicknesses to suit high-voltage and high-speed applications, respectively, while maintaining similar fabrication processes.
Innovation Solution
The integration of gate-all-around (GAA) devices with stacked nanosheet channels in both I/O and core areas, where the I/O devices have a thicker gate oxide layer than core devices, achieved through a fabrication method that includes forming gate dielectric layers and modulating thickness using annealing processes to accommodate varying voltage requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate oxide layer thickness is increased for I/O devices to support high-voltage applications, then device reliability is improved, but manufacturing complexity increases due to the need for different gate oxide thicknesses in different device regions
Solution Approach 1:
The patent applies local quality by forming different gate oxide layer thicknesses in different regions of the semiconductor device. Specifically, a first gate oxide layer with a first thickness is formed in a first region (for I/O devices requiring high-voltage support), while a second gate oxide layer with a second thickness is formed in a second region (for core devices requiring high-speed performance). This allows each region to have optimized gate oxide thickness tailored to its specific functional requirements, thereby improving device reliability without requiring complete redesign of the entire manufacturing process.
Solution Approach 2:
The patent segments the semiconductor device into multiple regions with different gate oxide layer configurations. The device is divided into a first region containing I/O devices with thicker gate oxide layers and a second region containing core devices with thinner gate oxide layers. This segmentation enables independent optimization of gate oxide thickness for different device types within the same semiconductor structure, resolving the contradiction between reliability (requiring thicker oxide for I/O) and manufacturing complexity (simplified by using a unified regional approach rather than device-by-device customization).
2Speed
If gate oxide layer thickness is decreased for core devices to support high-speed applications, then device speed is improved, but device reliability deteriorates due to reduced voltage tolerance
Solution Approach 1:
The patent implements local quality by providing different gate oxide layer thicknesses in different regions: thinner gate oxide layers in the second region (core devices) to enable high-speed operation, and thicker gate oxide layers in the first region (I/O devices) to ensure voltage tolerance and reliability. This localized optimization allows core devices to achieve improved speed performance while I/O devices maintain adequate voltage tolerance, resolving the contradiction between speed and reliability requirements.
3Adaptability or versatility
If different gate oxide layer thicknesses are used for I/O and core devices, then device performance is optimized for specific applications, but fabrication process complexity increases
Solution Approach 1:
The patent uses segmentation to divide the semiconductor device into distinct regions (first region for I/O devices, second region for core devices) that receive different gate oxide layer thicknesses during fabrication. This regional segmentation allows the fabrication process to optimize performance for specific applications in each region while maintaining a systematic and organized manufacturing approach, thereby improving adaptability without excessively increasing fabrication process complexity.
Solution Approach 2:
The patent applies local quality by forming gate oxide layers with different thicknesses in different regions of the semiconductor device during the fabrication process. The first gate oxide layer with first thickness is formed in the first region, and the second gate oxide layer with second thickness is formed in the second region. This approach enables device performance optimization for specific applications (high-voltage for I/O, high-speed for core) while using a unified fabrication methodology that processes different regions differently, thus improving adaptability while controlling fabrication process complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for flexible design integration of I/O and core devices with optimized gate oxide thicknesses, enhancing performance for high-voltage and high-speed applications while maintaining compatibility with existing semiconductor manufacturing flows.
Implementation Method 1
performing an annealing process to increase a thickness of the second oxide layer under the capping layer
Implementation Method 2
performing an annealing process to increase a thickness of the second oxide layer under the capping layer
Data Source
AI summary
A semiconductor device includes a first transistor located in a first region and a second transistor located in a second region. The first transistor includes first and second channel members vertically stacked above the substrate, and a first gate dielectric layer having a first portion wrapping around the first channel member and a second portion wrapping around the second channel member. The second transistor includes third and fourth channel member vertically stacked above the substrate and a second gate dielectric layer having a first portion wrapping around the third channel member and a second portion wrapping around the fourth channel member. The first and second channel members are thicker than the third and fourth channel members. A vertical distance between the first and second portions of the first gate dielectric layer is larger than a vertical distance between the first and second portions of the second gate dielectric layer.