Isolation Structure for Gate-All-Around Nanosheet Transistors
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, affecting production efficiency and cost.
Innovation Solution
The process involves forming fin structures and gate all-around transistor structures using double-patterning or multi-patterning techniques, with sacrificial layers and epitaxial growth, to create semiconductor device structures that allow for smaller pitches and improved etching selectivity, enabling the formation of reliable semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but fabrication process complexity and difficulty increase
Solution Approach 1:
The patent applies segmentation by dividing the fabrication process into multiple patterning steps (e.g., self-aligned double patterning, self-aligned triple patterning) to form features at smaller pitches. Instead of attempting to create all features in a single lithography step, the process segments the pattern formation into sequential steps using sacrificial layers and spacer formation, thereby enabling sub-10nm feature sizes while managing process complexity through systematic decomposition of the fabrication workflow.
Solution Approach 2:
The patent employs preliminary action through self-aligned processes where sacrificial layers are formed first, followed by spacer deposition that automatically defines the position of subsequent features. This preliminary placement of sacrificial structures enables precise alignment of critical features (such as gate and channel structures) without requiring additional alignment steps, thereby reducing overall process complexity while achieving smaller feature sizes.
2Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency and cost are improved, but manufacturing reliability deteriorates
Solution Approach 1:
The patent applies local quality by using different materials with distinct properties in different regions of the device structure. Specifically, sacrificial layers made of materials with appropriate etch selectivity (such as silicon oxide or silicon nitride) are placed in specific locations to protect underlying structures during etching processes. This localized material selection ensures that critical regions maintain their integrity while allowing aggressive etching elsewhere, thereby preserving device reliability at smaller dimensions.
Solution Approach 2:
The patent employs intermediary structures in the form of sacrificial layers that mediate between the lithography pattern and the final device structure. These intermediary sacrificial layers enable the formation of complex 3D structures (such as FinFETs or nanosheet transistors) by providing temporary support and alignment references during fabrication. The sacrificial layers are removed only after serving their protective and alignment functions, ensuring that the final structure maintains high reliability.
3Productivity
If smaller pitches are formed to increase functional density, then productivity is improved, but etching selectivity requirements increase
Solution Approach 1:
The patent employs composite material systems consisting of multiple layers with different etch selectivities. The structure includes sacrificial layers (e.g., silicon oxide), spacer materials (e.g., silicon nitride or silicon oxynitride), and underlying substrate materials, each engineered to have distinct etch response characteristics. This composite material approach enables selective removal of sacrificial layers and spacers in sequence using different etchants or etching conditions, thereby achieving the required etching selectivity for smaller pitches while maintaining high productivity through integrated process flows.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the formation of semiconductor devices by improving etching selectivity and reducing complexity, leading to more efficient and cost-effective production of smaller, more complex circuits.
Implementation Method 1
epitaxial growth
Data Source
AI summary
A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor fin over a substrate and multiple semiconductor nanostructures suspended over the semiconductor fin. The semiconductor device structure also includes a gate stack extending across the semiconductor fin, and the gate stack wraps around each of the semiconductor nanostructures. The semiconductor device structure further includes a first epitaxial structure and a second epitaxial structure sandwiching the semiconductor nanostructures. In addition, the semiconductor device structure includes an isolation structure between the semiconductor fin and the gate stack. The isolation structure extends exceeding opposite sidewalls of the first epitaxial structure.