GAA Nanosheet Transistor Structure for Short-Channel Leakage Control
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Solution Overview
Problem
The semiconductor industry faces challenges in scaling down semiconductor manufacturing processes while minimizing short channel effects and leakage currents, which are exacerbated by the increasing complexity and size reduction of integrated circuits.
Innovation Solution
The method involves forming a gate-all-around (GAA) transistor device with a gate structure wrapping around nanostructures, using a stack of semiconductor layers with different materials for selective etching and oxidation rates, and forming epitaxial structures and isolation structures to control channel current flow and reduce short channel effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but short channel effects and leakage currents increase
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional FinFET structures with vertical channels. The fin structure extends into the third dimension (depth), providing gate control from multiple surfaces (top and sidewalls) rather than just one surface, thereby improving electrostatic control and reducing short channel effects at scaled dimensions
Solution Approach 2:
The gate structure is wrapped around the fin channel in a gate-all-around configuration, with the gate enclosing the channel from multiple directions. This nested arrangement provides superior electrostatic control over the channel current compared to conventional planar gates, effectively suppressing short channel effects and leakage currents
2Productivity
If geometry size is decreased to increase functional density, then more circuits can be integrated, but leakage currents increase
Solution Approach 1:
By creating vertical fin structures that extend into the depth dimension, the patent achieves higher functional density within the same planar footprint while the three-dimensional gate control suppresses leakage currents through improved electrostatic management of the channel
Solution Approach 2:
The patent employs selective doping profiles with different doping concentrations at different locations within the fin structure and surrounding regions. This local variation in doping quality allows optimization of carrier concentration and electric field distribution to minimize leakage currents while maintaining high functional density
3Ease of manufacture
If conventional planar transistors are used, then manufacturing is simpler, but control over channel current flow is insufficient at scaled dimensions
Solution Approach 1:
The patent employs selective doping profiles with different doping concentrations at different locations within the fin structure and surrounding regions. This local variation in doping quality allows optimization of carrier concentration and electric field distribution to minimize leakage currents while maintaining high functional density
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of semiconductor devices by reducing short channel effects and leakage currents, enabling more efficient and complex circuit designs with improved control over channel current flow.
Implementation Method 1
using a stack of semiconductor layers with different materials for selective etching and oxidation rates
Implementation Method 2
using a stack of semiconductor layers with different materials for selective etching and oxidation rates
Data Source
AI summary
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes semiconductor nanosheets vertically stacked upon one another and disposed above a semiconductor substrate, a gate structure surrounding each of the semiconductor nanosheets, and source/drain regions disposed over the semiconductor substrate and laterally abutting the semiconductor nanosheets. The semiconductor nanosheets serve as channel regions, and a topmost semiconductor nanosheet most distanced from the semiconductor substrate is thinner than an underlying semiconductor nanosheet between the topmost semiconductor nanosheet and the semiconductor substrate.