GAA Nanosheet Source/Drain Liner for Void and Strain Control
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Solution Overview
Problem
The scaling down of integrated circuits has increased complexity in processing and manufacturing, particularly for multi-gate devices like FINFETs and GAA transistors, where challenges include void defects and strain retention in the channel regions, which affect device performance.
Innovation Solution
A liner layer is formed to line the bottom surface and sidewalls of the source/drain regions, sandwiched between the semiconductor nanosheets and the gate stack, facilitating epitaxial growth of the source/drain regions to control their height and shape, reducing void defects and enhancing strain retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate devices are introduced to replace planar transistors, then functional density is improved, but processing complexity and manufacturing challenges increase
Solution Approach 1:
The patent segments the source/drain structure into multiple discrete components: sacrificial nanosheets, spacer structures, and epitaxially grown source/drain regions. This segmentation allows independent optimization of each component and simplifies the overall manufacturing process by breaking down the complex multi-gate device formation into manageable sequential steps
Solution Approach 2:
The patent employs preliminary actions by forming sacrificial nanosheets and spacer structures before the actual source/drain region formation. These preliminary structures serve as templates and guides that simplify subsequent epitaxial growth processes, ensuring precise positioning and dimensional control of the final source/drain regions
2Reliability
If source/drain regions are formed in multi-gate devices, then device functionality is achieved, but void defects occur affecting performance
Solution Approach 1:
The patent introduces liner layers as intermediary structures between the sacrificial nanosheets/spacers and the epitaxially grown source/drain regions. These liner layers act as mediators that facilitate uniform epitaxial growth, ensure proper interface formation, and prevent void defect generation by providing a consistent nucleation surface for the source/drain material
Solution Approach 2:
The patent utilizes parameter changes in the epitaxial growth process, controlling temperature, pressure, and gas flow conditions to optimize source/drain region formation. By precisely adjusting these parameters, the process achieves complete coverage and uniform thickness while preventing void defect formation during the growth of source/drain regions
3Ease of manufacture
If source/drain regions are formed without proper control, then manufacturing is simplified, but strain retention in channel regions is lost affecting performance
Solution Approach 1:
The patent applies local quality by forming source/drain regions with specific epitaxial growth conditions that are tailored to different locations within the device structure. The liner layers and spacer structures enable localized control of strain characteristics in the channel regions, ensuring optimal strain retention where needed while maintaining manufacturing feasibility through standardized process steps
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution improves etching resistance and reduces void defects while maintaining strain in the channels, thereby enhancing the performance of multi-gate transistors.
Implementation Method 1
facilitating epitaxial growth of the source/drain regions to control their height and shape
Data Source
AI summary
Provided are a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a plurality of semiconductor nanosheets, a source/drain (S/D) region, a gate stack, and a liner layer. The substrate includes at least one fin. The plurality of semiconductor nanosheets are stacked on the at least one fin. The S/D region abuts the plurality of semiconductor nanosheets. The gate stack wraps the plurality of semiconductor nanosheets. The liner layer lines a bottom surface and a sidewall of the S/D region and is sandwiched between the S/D region and the gate stack.