GAA Nanosheet Gate Structure With Local Doping for Higher Current
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Solution Overview
Problem
As semiconductor technology advances and transistor dimensions shrink below a few nanometers, FinFETs face challenges such as short-channel effects, leakage, and material limitations, making it difficult to manufacture, while Gate-All-Around (GAA) devices offer a new direction with a four-side wrapped channel, but still face issues like low doping ion concentration affecting device performance.
Innovation Solution
A semiconductor structure and method involving a substrate with composite layers, interlayer dielectric, gate trenches, and doping regions are formed to increase doping ion concentration under the gate sidewall, reducing resistance and improving operating current by doping dopants in the initial composite layer before forming the gate sidewall and removing the dummy gate dielectric layer to prevent conduction between the source-drain and gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If transistor dimension is shrunk to below a few nanometers, then higher operating current and greater short-channel suppression capability are achieved, but manufacturing difficulty increases and leakage occurs
Solution Approach 1:
The channel is divided into multiple segments stacked vertically to form nanosheet structures, allowing the gate to control multiple channel segments simultaneously. This segmentation enables continued scaling and improved current drive while maintaining manufacturability through modular fabrication processes.
Solution Approach 2:
The transistor structure transitions from a planar two-dimensional channel to a three-dimensional vertically-stacked nanosheet channel. This dimensional change allows the gate to wrap around the channel on three sides (gate-all-around), providing superior electrostatic control and short-channel suppression at scaled dimensions.
2Power
If transistor dimension is shrunk to below a few nanometers, then higher operating current is achieved, but leakage increases
Solution Approach 1:
High-concentration doping regions are formed in the nanosheet channels before final device assembly. This preliminary doping action creates strong potential wells that suppress band-to-band tunneling leakage currents, enabling the device to achieve high operating current with reduced leakage at scaled dimensions.
Solution Approach 2:
The doping concentration parameter is dramatically increased in the nanosheet channels to create heavily-doped regions. This parameter change transforms the electrical characteristics, forming strong accumulation layers that suppress off-state leakage while maintaining on-state current drive capability.
3Power
If doping ion concentration is increased, then operating current is enhanced, but resistance in neighboring regions increases
Solution Approach 1:
The doping structure is designed with spatially varying concentrations: high doping concentration is localized specifically in the nanosheet channel regions to enhance carrier density and operating current, while low doping concentration is maintained in the surrounding matrix and contact regions to ensure low series resistance. This local quality differentiation resolves the contradiction between current enhancement and resistance control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The increased doping ion concentration reduces neighboring region resistance, enhancing the operating current and overall performance of the GAA device.
Implementation Method 1
The doping region formed under the gate sidewall can be used to increase the doping ion concentration in the neighboring region of the channel layer and the source-drain layer
Data Source
AI summary
A semiconductor structure includes a plurality of composite layers formed on a portion of a substrate. An interlayer dielectric layer is formed on the substrate and the plurality of composite layers. A first gate trench is formed on the interlayer dielectric layer, and a gate sidewall is formed on a side surface of the first gate trench. The composite layer includes stacked channel layers and a second gate trench between neighboring channel layers. The first gate trench and the gate sidewall cross over a portion of a sidewall and a portion of a top surface of the composite layer, and the first gate trench communicates with the second gate trench. A gate is formed in the first and second gate trenches. The doping region is formed in a channel layer. The source-drain layer is formed in the composite layer on two sides of the gate structure.