GAA Nanosheet Semiconductor Layout for Dense Multi-Patterning
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Solution Overview
Problem
The semiconductor manufacturing process faces increased complexity due to the scaling down of ICs, requiring advancements in manufacturing processes to maintain efficiency and reduce costs.
Innovation Solution
The implementation of gate all around (GAA) transistor structures, which are patterned using photolithography and self-aligned processes, allowing for smaller pitch creation and improved control of channel current flow, along with the use of multi-patterning processes to form semiconductor devices on various substrates, including bulk silicon, silicon-on-insulator, and Group III-V semiconductors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency is improved and costs are lowered, but manufacturing process complexity increases
Solution Approach 1:
The manufacturing process is divided into multiple patterning steps (e.g., self-aligned double patterning, self-aligned quadruple patterning) where each step creates a portion of the final pattern. This segmentation allows achievement of smaller pitch sizes without requiring a single complex lithography step, thereby maintaining productivity while managing process complexity through modular fabrication steps.
Solution Approach 2:
The patent transitions from planar transistor structures to three-dimensional gate-all-around (GAA) nanosheet structures. This dimensional change enables continued scaling and functional density improvement by utilizing vertical space and multiple wrapping gates, effectively increasing integration density while managing the complexities associated with smaller geometry sizes.
2Quantity of substance
If functional density is increased by scaling down, then more devices fit per chip area, but the manufacturing process becomes more complex
Solution Approach 1:
Multiple semiconductor layers are stacked vertically to form nanosheets, with each layer containing functional devices. This nesting approach increases the number of devices per chip area by utilizing the vertical dimension, allowing higher functional density without proportionally increasing lateral manufacturing complexity.
Solution Approach 2:
Semiconductor layers are grown epitaxially on patterned substrates before final device formation. This preliminary structuring enables subsequent self-aligned patterning processes to achieve high-density device arrangements with reduced alignment complexity, as the vertical stacking and lateral patterns are established in coordinated sequence rather than requiring complex post-processing alignment.
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, at least two source/drain features, at least two source/drain features, one or more channel layers, a gate structure, a first conductive feature, a second conductive feature, and an alignment mark. The semiconductor substrate has a first region and a second region next to the first region. The at least two source/drain features are disposed in the second region and are laterally arranged to each other. The one or more channel layers are disposed in the second region and connect the at least two source/drain features. The gate structure is disposed in the second region and engages the one or more channel layers and interposes the at least two source/drain features. The first conductive feature is disposed in the second region and is electrically coupled to the at least two source/drain features. The second conductive feature is disposed in the second region and is electrically coupled to the at least two source/drain features through the first conductive feature. The alignment mark is disposed in the first region and includes a first dielectric feature and a third conductive feature lining a bottom and a sidewall of the first dielectric feature.