GAA Nanosheet Parasitic Capacitance Reduction

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Solution Overview

Problem

Gate-all-around (GAA) semiconductor devices face performance degradation due to parasitic capacitance between the gate structure and source/drain contacts, which increases as the width of nanosheets decreases, leading to slower speed and frequency.

Innovation Solution

A dielectric structure is disposed between the nanosheet stack structures to reduce capacitive coupling and parasitic capacitance, improving performance by depositing a dielectric material that removes capacitive coupling from the source/drain contacts to the gate structure.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the width of nanosheets is decreased to increase transistor density, then transistor density is improved, but parasitic capacitance increases leading to slower speed and frequency

Engineering Contradiction:

Improvetransistor densityVSAvoiddevice speed and frequency

Core Design Contradiction:

Quantity of substanceVSSpeed

Solution Approach 1:

A dielectric structure is introduced as an intermediary element positioned between adjacent nanosheet stack structures. This dielectric material acts as a mediator that reduces parasitic capacitance between the gate structure and source/drain contacts, thereby improving device speed and frequency while maintaining high transistor density achieved through narrow nanosheet widths.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Speed

If a dielectric structure is added between nanosheet stack structures to reduce parasitic capacitance, then device speed and frequency are improved, but device complexity increases

Engineering Contradiction:

Improvedevice speed and frequencyVSAvoidstructure complexity

Core Design Contradiction:

SpeedVSDevice complexity

Solution Approach 1:

The patent modifies the electrical parameters of the device by introducing a dielectric structure with specific permittivity characteristics. This parameter change reduces parasitic capacitance values between gate and source/drain regions, thereby improving switching speed and frequency without requiring fundamental redesign of the device architecture.

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The introduction of a dielectric structure between the nanosheet stack structures effectively reduces parasitic capacitance, enhancing the speed and performance of GAA semiconductor devices by minimizing capacitive coupling, allowing for increased transistor density and performance.

Implementation Method 1

parasitic capacitance between the gate structure and source/drain contacts

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

A dielectric structure is disposed between the nanosheet stack structures to reduce capacitive coupling and parasitic capacitance

Methodology Applied

Scientific EffectDielectric: Dielectric

Data Source

PatentUS11189617B2Gate-all-around devices with reduced parasitic capacitance

Publication Date: 2021.11.30 QUALCOMM INC

AI summary

Certain aspects of the present disclosure generally relate to a gate-all-around (GAA) semiconductor device. The GAA semiconductor device generally includes a substrate, a first nanosheet stack structure, a second nanosheet stack structure, the first and second nanosheet stack structures being disposed above a horizontal plane of the substrate and each comprising one or more nanosheet structures, and a dielectric structure disposed between the first nanosheet stack structure and the second nanosheet stack structure.