Gate-All-Around Nanosheet Structure for Low-Capacitance Source/Drain Scaling
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Solution Overview
Problem
Existing gate-all-around (GAA) devices face challenges in reducing parasitic capacitance and preventing source/drain structure defects due to lateral merging, which hinders the scaling of IC technologies and affects transistor performance.
Innovation Solution
The use of sidewall spacers, promoted by an extra semiconductor layer, confines the lateral growth of source/drain structures, reducing parasitic capacitance and preventing defects, while omitting dielectric fins to facilitate gate replacement processes, thereby enhancing transistor switching speed and density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If source/drain structures are allowed to grow laterally to increase transistor density, then device density improves, but parasitic capacitance increases and defects from lateral merging occur
Solution Approach 1:
The patent divides the source/drain structure into discrete, confined regions using sidewall spacers as boundaries. Each source/drain structure is segmented and isolated from adjacent structures, preventing lateral merging while maintaining high density through controlled positioning rather than continuous growth.
Solution Approach 2:
The patent applies different properties to different regions: sidewall spacers provide lateral confinement with specific thickness and material properties, while source/drain structures maintain optimized dimensions for electrical performance. This local differentiation allows density improvement without proportional increase in parasitic capacitance.
2Reliability
If dielectric fins are used to prevent lateral merging of source/drain structures, then defect prevention improves, but gate replacement processes become more difficult
Solution Approach 1:
The patent removes dielectric fins from the structure and replaces their confinement function with sidewall spacers. This extraction eliminates the manufacturing complexity associated with dielectric fin integration while maintaining the essential function of preventing lateral merging through the sidewall spacer-based confinement approach.
Solution Approach 2:
The sidewall spacers serve as an intermediary structure that performs the dual function of lateral confinement and gate definition. Rather than using separate dielectric fins for confinement and gates for definition, the sidewall spacers mediate both functions, simplifying the overall manufacturing process including gate replacement operations.
3Productivity
If IC dimensions are reduced to improve production efficiency and lower costs, then productivity improves, but manufacturing process complexity increases
Solution Approach 1:
The sidewall spacers are formed through self-aligned processes where the spacer material automatically conforms to the fin or nanosheet sidewalls. This self-service approach eliminates the need for separate alignment and positioning steps, maintaining manufacturing simplicity despite aggressive scaling to smaller dimensions.
Solution Approach 2:
The patent transitions from two-dimensional planar scaling to three-dimensional vertical structures with sidewall spacers providing confinement in the lateral dimension while allowing vertical growth. This dimensional change enables continued scaling and productivity improvement without proportionally increasing process complexity, as the spacer formation follows the vertical geometry naturally.
Data Source
AI summary
A method includes providing a substrate, an isolation structure, and a fin extending from the substrate and through the isolation structure. The fin includes a stack of layers having first and second layers that are alternately stacked and have first and second semiconductor materials respectively. A topmost layer of the stack is one of the second layers. The structure further has a sacrificial gate stack engaging a channel region of the fin. The method further includes forming gate spacers and forming sidewall spacers on sidewalls of the fin in a source/drain region of the fin, wherein the sidewall spacers extend above a bottom surface of a topmost one of the first layers. The method further includes etching the fin in the source/drain region, resulting in a source/drain trench; partially recessing the second layers exposed in the source/drain trench, resulting in gaps; and forming dielectric inner spacers inside the gaps.