GAA Nanosheet FET SDE Doping for Abrupt Junction Control
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Solution Overview
Problem
Existing gate-all-around (GAA) transistors face challenges in achieving precise abrupt junction profiles for source/drain extensions (SDEs) due to rapid diffusion and small spacer separations, leading to variations in junction depth and potential gate leakage paths, which degrade transistor performance.
Innovation Solution
A semiconductor device with an abrupt overlapped SDE structure is developed, featuring vertically stacked nanosheets with a discrete source and drain region, where the SDE exhibits a sharp dopant profile transition from low to high doping levels, maintaining consistency across the nanosheet vertical dimension.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional doping methods are used for source/drain extensions in GAA transistors, then doping can be achieved, but rapid diffusion and small spacer separations lead to variations in junction depth and potential gate leakage paths
Solution Approach 1:
The source/drain extension is segmented into multiple regions with different doping concentrations along the channel direction. A first doped region is positioned closer to the channel with a first doping concentration, while a second doped region is positioned farther from the channel with a second doping concentration. This segmentation allows precise control of dopant distribution and prevents rapid diffusion into the channel, thereby achieving abrupt junction profiles and preventing gate leakage paths.
Solution Approach 2:
Different regions of the source/drain extension are assigned different doping concentrations based on their local functional requirements. The region closer to the channel has a lower doping concentration to prevent leakage, while the region farther away has a higher doping concentration for good electrical contact. This local quality differentiation enables precise control of electrical characteristics and prevents harmful effects throughout the device.
2Reliability
If source/drain regions are heavily doped to reduce resistance, then electrical conductivity improves, but hot carrier effects increase which degrades transistor scalability and reliability
Solution Approach 1:
The doping concentration parameter is changed gradually from the channel interface toward the contact region. By implementing a doping gradient with lower concentration near the channel and higher concentration at the contact, the patent reduces peak electric fields that cause hot carrier effects while maintaining low resistance for good electrical contact. This parameter optimization enables transistor scalability without suffering from hot carrier degradation.
3Productivity
If gate length is reduced to improve transistor scaling, then device density increases, but short-channel effects become more pronounced which degrades electrostatic control
Solution Approach 1:
The patent transitions from planar doping to three-dimensional dopant distribution around the nanosheet channel. By forming source/drain extensions that wrap around the channel in multiple dimensions and implementing vertical doping gradients, the patent achieves superior electrostatic control over the channel potential. This multi-dimensional doping approach allows reduced gate length for higher device density while maintaining effective electrostatic control and minimizing short-channel effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design optimizes electrical characteristics by minimizing short-channel effects, reducing leakage currents, and improving transistor reliability and performance through precise dopant control.
Implementation Method 1
portions of the SDE in vicinity of the source/drain region are doped with a first dopant
Implementation Method 2
the doped portions of SDE are doped with a drive-in anneal along a direction orthogonal to the gate channel
Data Source
AI summary
A semiconductor device includes a source/drain region adjacent to a gate channel, a plurality of nanosheets extended vertically at the gate channel, and a source/drain extension (SDE) between the source/drain region and the plurality of nanosheets. Portions of the SDE in vicinity of the source/drain region are doped with a first dopant.