GAA Nanosheet IC Structure With Integrated Seal Ring Alignment
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Solution Overview
Problem
The development of three-dimensional designs, such as multi-gate field effect transistors (FETs), particularly gate-all-around (GAA) FETs, faces challenges in fabrication and design due to issues like short-channel effects and drain induced barrier lowering, which are not adequately addressed by existing technologies.
Innovation Solution
The integration of nanosheet structures for alignment marks and seal rings in the fabrication process of multi-gate devices, utilizing epitaxial layers and specific etching processes to form fins and isolation structures, allows for better process control and cost efficiency by integrating with nanosheet device fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If separate fabrication processes are used for alignment marks and seal rings, then process control and manufacturing precision are maintained, but manufacturing complexity and cost increase
Solution Approach 1:
The patent combines the fabrication of alignment marks and seal rings with the nanosheet device fabrication process into a single integrated process. Alignment marks and seal rings are formed using the same epitaxial growth and etching steps as the nanosheet devices, eliminating separate fabrication processes and reducing overall manufacturing complexity while maintaining structural integrity
2Manufacturing precision
If conventional fabrication processes are used, then manufacturing simplicity is maintained, but line collapse occurs and manufacturing precision deteriorates
Solution Approach 1:
The patent modifies fabrication parameters by using specific epitaxial growth conditions and etching parameters optimized for nanosheet structures. The multi-epitaxial layer structure with controlled thicknesses and compositions enables precise control over fin formation and line collapse prevention during etching, achieving high manufacturing precision through parameter optimization
3Reliability
If gate-all-around FET structure is implemented, then device performance is improved, but fabrication difficulty increases
Solution Approach 1:
The patent segments the channel region into multiple thin nanosheet layers separated by sacrificial layers. This segmentation enables the gate to wrap around all surfaces of each nanosheet channel, achieving the gate-all-around structure that provides superior electrostatic control and device performance while simplifying the fabrication process through modular layer formation
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach achieves improved process control with reduced line collapse and cost savings by integrating alignment mark and seal ring fabrication with nanosheet device processes, enhancing the performance of multi-gate devices.
Implementation Method 1
patterning the epitaxial stack into a first fin and a second fin
Implementation Method 2
forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately arranged over the semiconductor substrate
Data Source
AI summary
A method for fabricating an integrated circuit structure is provided. The method includes forming an epitaxial stack over a semiconductor substrate, wherein the epitaxial stack comprises a plurality of first epitaxial layers and a plurality of second epitaxial layers alternately arranged over the semiconductor substrate; patterning the epitaxial stack into a first fin and a second fin, wherein from a top view the first fin extends along a first direction, and the second fin has a first fin line extending along the first direction and a second fin line extending along a second direction different from the first direction; forming a first gate structure over a first portion of the first fin; etching a recess in a second portion of the first fin adjacent the first portion of the first fin; and forming a source/drain feature in the recess.