GAA Nanosheet Fabrication With SiGe Wrapping for Gate Uniformity
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Solution Overview
Problem
The fabrication of gate-all-around (GAA) structures in ultra-large-scale integrated circuits faces challenges such as inconsistency in gate lengths, channel edge roughness, and parasitic capacitance due to high-aspect-ratio etching processes, which damage the sidewall of the superlattice Fin and result in high-resistance metal areas.
Innovation Solution
A method is developed to reduce the aspect ratio of the dummy gate by selective epitaxy growth of a SiGe layer and chemical mechanical polishing (CMP) to form a SiGe stacked structure, followed by patterning and etching processes that minimize damage and improve uniformity, reducing parasitic capacitance through the use of epitaxial SiGe for all-around gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional patterning and etching of dummy gate is performed, then the gate structure is formed, but the large aspect ratio leads to inconsistency in gate lengths and large roughness in pattern edge
Solution Approach 1:
The SiGe layer is grown preliminarily before dummy gate formation to create a sacrificial structure. This preliminary action enables subsequent planarization and dummy gate patterning to proceed on a flattened surface, reducing the aspect ratio and improving gate length consistency while minimizing edge roughness
Solution Approach 2:
The method changes the physical state and geometry parameters by growing an epitaxial SiGe layer that is subsequently planarized through CMP. This parameter change transforms the high-aspect-ratio structure into a low-aspect-ratio structure, enabling precise dummy gate patterning
2Ease of manufacture
If high-aspect-ratio etching is used to remove dummy gate, then the dummy gate is removed, but the sidewall of the superlattice Fin is damaged
Solution Approach 1:
An epitaxial SiGe layer serves as an intermediary sacrificial structure during dummy gate removal. This intermediary layer can be selectively removed without damaging the underlying superlattice Fin sidewalls, as it provides a buffer zone that protects the critical Fin structures during the etching process
Solution Approach 2:
The method converts the potential harm of high-aspect-ratio etching into a benefit by using the epitaxial SiGe layer as a protective sacrificial material. The SiGe layer absorbs the etching damage that would otherwise affect the Fin sidewalls, and can be selectively removed afterward
3Ease of manufacture
If titanium nitride is used to fill the metal gate in dummy gate trench, then the gate is formed, but high-resistance areas and parasitic capacitance are created
Solution Approach 1:
The dummy gate structure is completely removed after serving its purpose as a placeholder and alignment reference. This extraction of the dummy gate eliminates the source of parasitic capacitance between the dummy-gate trench sidewalls and adjacent metal gates, while the actual gate structure is formed separately with optimal material composition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the consistency of gate lengths, reduces channel edge roughness, and decreases parasitic capacitance, leading to improved performance and speed of nanosheet devices by minimizing damage and resistance areas.
Implementation Method 1
performing selective epitaxy growth of a SiGe layer on the at least two active regions to form a SiGe-wrapped stacked structure
Implementation Method 2
after the backfilling of silicon oxide and chemical mechanical polishing (CMP), an amorphous-silicon dummy-gate CMP process is conducted on a flat top to reduce the aspect ratio of the dummy gate
Data Source
AI summary
A method for fabricating a gate-all-around (GAA) structure, including: etching a superlattice laminate to form active regions; performing selective epitaxy growth of a silicon germanium (SiGe) layer to form a SiGe-wrapped Si nanosheet stacked structure, where the SiGe layer and the SiGe/Silicon (Si) periodic superlattice laminate have the same germanium (Ge) content; after silicon oxide is backfilled and chemical mechanical polishing (CMP) is performed on the active regions, performing an amorphous-silicon dummy-gate process on a top of the active regions; removing dummy gate, and selectively etching the SiGe layer; and forming hole-trench structures connected with trenches of the dummy gate around the Si nanosheet stacked structure.