Stacked GAA Nanosheet Structure for Void-Free Source/Drain Growth
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Solution Overview
Problem
Conventional gate-all-around (GAA) transistor fabrication faces challenges such as poor epitaxial growth in the source/drain region, small formation margin for gate dielectric and electrode in narrow channel-channel spaces, and increased capacitance between adjacent conductive regions, exacerbated by device scaling down.
Innovation Solution
A bottom-up epitaxial growth process is employed to form source/drain regions without voids, with a large formation margin for gate dielectric and electrode, and decreased capacitance between source/drain and active gate structures through a method involving selective etching and conformal epitaxial growth in tapered trenches.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional GAA device fabrication methods are used, then gate control is improved through gate-all-around structure, but epitaxial growth in source/drain region deteriorates with poor growth quality and void formation
Solution Approach 1:
The method performs preliminary actions by forming sacrificial nanowire structures and defining trench geometries before epitaxial growth. The tapered trench profile is pre-established through selective etching of alternating nanowire layers, creating optimal growth conditions that prevent void formation during subsequent source/drain epitaxial deposition
Solution Approach 2:
The invention changes the geometric parameters of the epitaxial growth environment by creating tapered trenches with specific angle ranges (30-60 degrees). This parameter modification optimizes the growth front progression and material deposition kinetics, ensuring high-quality epitaxial growth without voids in the source/drain regions
2Productivity
If device size is scaled down to increase functional density, then production efficiency is improved, but formation margin for gate dielectric and electrode deteriorates in narrow channel-channel spaces
Solution Approach 1:
The invention transitions from two-dimensional planar scaling to three-dimensional vertical structuring by forming stacked nanosheet channels with gate-all-around configuration. This dimensional change allows continued scaling benefits while providing adequate formation margins through the vertical stacking approach, where multiple channels are arranged in the vertical dimension rather than competing for lateral space
Solution Approach 2:
The channel region is segmented into multiple discrete nanosheets stacked vertically, with gate dielectric and electrode structures formed around each segment. This segmentation allows independent formation and optimization of each channel layer, providing sufficient formation margin even as individual channel dimensions are reduced for scaling
3Length of moving object
If conventional fabrication processes are used for scaling, then device miniaturization is achieved, but capacitance between adjacent conductive regions increases
Solution Approach 1:
The invention introduces dielectric materials as intermediary layers between adjacent conductive regions, specifically between source/drain regions and gate structures. These intermediary dielectric layers act as electrical isolators that reduce parasitic capacitance coupling, allowing device miniaturization without the harmful increase in inter-regional capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method ensures void-free source/drain regions, ample formation margin for gate dielectric and electrode, and reduced capacitance, enhancing the performance and manufacturability of GAA devices.
Implementation Method 1
A bottom-up epitaxial growth process is employed to form source/drain regions without voids
Data Source
AI summary
The present disclosure provides an integrated circuit (IC) device, including: a semiconductor substrate having a top surface; a first source/drain feature and a second source/drain feature disposed on the semiconductor substrate; and a plurality of semiconductor layers including a first semiconductor layer and a second semiconductor layer. Each of the first semiconductor layer and the second semiconductor layer extends longitudinally in a first direction and connects the first source/drain feature and the second source/drain feature. The first semiconductor layer is stacked over the second semiconductor layer in a second direction perpendicular to the first direction. A length of the first semiconductor layer along the first direction is less than a length of the second semiconductor layer along the first direction. The IC device further includes a gate structure engaging center portions of the first semiconductor layer and the second semiconductor layer.