GAA Nanosheet Enlargement for Lower Source-Drain Resistance
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise with the integration of electronic components, including defects in source and drain regions, increased electrical resistance, and current crowding at interfaces, which affect performance and efficiency.
Innovation Solution
The formation of inner spacers between stacked semiconductor layers in nano-FETs, accompanied by epitaxial growth of source and drain regions on semiconductor material, enhances surface area contact and reduces defects, improving current flow and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but defects in source and drain regions increase and electrical resistance increases
Solution Approach 1:
The patent segments the source and drain regions into multiple discrete semiconductor nanosheets stacked vertically, creating a multi-layered structure. This segmentation allows each nanosheet to be independently formed and controlled, reducing defects that would propagate through a continuous structure while maintaining high integration density through vertical stacking.
Solution Approach 2:
The patent transitions from a planar two-dimensional structure to a three-dimensional vertically-stacked structure. By stacking multiple semiconductor nanosheets in the vertical dimension, the patent achieves higher integration density without further reducing the lateral feature size, thereby avoiding the associated defects and resistance increases.
2Productivity
If minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but current crowding at interfaces increases
Solution Approach 1:
The patent moves the current flow path from a two-dimensional planar interface to a three-dimensional vertical stacking configuration. Multiple nanosheets provide parallel current paths distributed across the vertical dimension, dispersing current density and eliminating crowding at any single interface while achieving higher integration density.
Solution Approach 2:
The current path is segmented into multiple discrete channels through the stacked nanosheets. Each nanosheet provides a separate current conduction path, distributing the total current across multiple interfaces rather than concentrating it at a single planar interface, thereby reducing current crowding effects.
3Ease of manufacture
If conventional deposition and lithography are used to fabricate semiconductor devices, then manufacturing process is simple, but manufacturing precision deteriorates at reduced feature sizes
Solution Approach 1:
The patent employs self-aligned fabrication processes where each layer is automatically positioned relative to previous layers without requiring additional alignment steps. The semiconductor nanosheets are formed in a self-aligned manner within the recesses, eliminating complex alignment procedures and maintaining high precision at reduced feature sizes while keeping the manufacturing process relatively simple.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in more efficient semiconductor devices with fewer defects, lower electrical resistance, and reduced current crowding, leading to a 5-10% saturation current gain.
Implementation Method 1
An epitaxial region is then formed over the substrate and the exposed portions of the third semiconductor layer
Data Source
AI summary
A method of forming a semiconductor device includes forming a fin of alternating layers of semiconductor nanostructures and sacrificial layers, laterally etching sidewall portions of the sacrificial layers, and depositing additional semiconductor material over the sidewalls of the semiconductor nanostructures and sacrificial layers. Following deposition of a dielectric material over the additional semiconductor material and additional etching, the remaining portions of the semiconductor structures and additional semiconductor material collectively form a hammer shape at each opposing side of the fin. Epitaxial source/drain regions formed on the opposing sides of the fin will contact the heads of the hammer shapes.