GAA Nanosheet Gate Structure With Strained Layers for Scaled Transistors
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Solution Overview
Problem
As semiconductor integrated circuits (ICs) scale down to smaller geometries, challenges arise in maintaining functional density and efficiency, particularly in forming gate stacks for advanced transistors like FinFETs and gate-all-around (GAA) devices.
Innovation Solution
The method involves forming a semiconductor device with a gate-all-around (GAA) transistor structure, where nanosheets are patterned and strained layers are grown to enhance performance. This includes forming a semiconductor stack with alternating SiGe and Si layers, patterning the stack to create nanosheet stacks, and growing strained layers to strain the nanosheets.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If semiconductor geometry is scaled down to increase functional density, then production efficiency and cost are improved, but manufacturing precision and device performance deteriorate
Solution Approach 1:
The patent segments the gate structure into multiple thin layers (first gate layer, second gate layer, third gate layer) instead of using a single thick gate. This segmentation allows each layer to be formed with precise thickness control through sequential deposition processes, thereby maintaining manufacturing precision while enabling scaled-down device geometries for increased functional density.
Solution Approach 2:
The patent transitions from planar gate structures to three-dimensional gate-all-around (GAA) nanosheet structures. By wrapping the gate electrodes around the nanosheet channels in multiple dimensions, the device achieves superior electrostatic control and enhanced performance at scaled geometries, resolving the contradiction between scaling down and maintaining manufacturing precision.
2Productivity
If gate stack complexity is increased for advanced transistor performance, then device efficiency is improved, but device complexity and fabrication difficulty increase
Solution Approach 1:
The patent applies different materials with specific properties to different regions of the gate stack: the first gate layer uses a different material than the second and third gate layers, and the nanosheet channels have specific crystal orientations. This local differentiation optimizes device performance in critical regions while managing overall complexity through targeted material selection rather than uniform complex structures.
Solution Approach 2:
The gate stack employs composite material structures with multiple gate layers made of different materials (e.g., metal gates, metal silicides) combined with semiconductor nanosheets. This composite approach enables tailored electrical and mechanical properties for enhanced device efficiency while providing a systematic framework to manage the complexity of advanced transistor architectures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of high-performance semiconductor devices with improved functional density and efficiency, addressing the scaling challenges faced in advanced transistor technologies.
Implementation Method 1
growing strained layers to strain the nanosheets
Data Source
AI summary
A semiconductor device includes a plurality of first nanosheets of a first conductive type, a plurality of second nanosheets of a second conductive type and a gate structure. The gate structure wraps the first nanosheets and the second nanosheets, wherein a first thickness of at least one of the first nanosheets is smaller than a second thickness of at least one of the second nanosheets.