GAA Nanosheet Channel Thickness Tuning for Current Crowding
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Solution Overview
Problem
As semiconductor devices approach the 5 nm technology node and below, the integration of horizontal gate-all-around (GAA) transistors faces challenges in reducing feature sizes while maintaining device performance, particularly in mitigating short channel effects and optimizing channel thickness for improved current crowding and strain effects.
Innovation Solution
The method involves forming a vertical stack of channels with a topmost channel thicker than the other channels, using a multi-layer deposition process of alternating semiconductor materials, and subsequent patterning and etching to create nanostructures with varying thicknesses, allowing for enhanced gate dielectric and electrode formation, which mitigates top channel current crowding and enables tuning of On-current and drain induced barrier loading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the minimum feature size is reduced to improve integration density, then more components can be integrated into a given area, but short channel effects worsen and device performance deteriorates
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional vertical nanosheet channels stacked in multiple layers. This dimensional change allows the channel to extend vertically above the gate electrode, increasing the effective channel area and integration density while maintaining sufficient gate control over the current flow path, thereby mitigating short channel effects that plague scaled 2D devices.
Solution Approach 2:
The patent implements gate-all-around structures where the gate electrode completely surrounds each vertical nanosheet channel in three dimensions. This nested configuration provides maximum gate control over the channel from all directions (top, bottom, and sidewalls), effectively suppressing short channel effects and enabling reliable operation at reduced feature sizes while maintaining high integration density.
2Reliability
If the channel thickness is reduced to improve gate control, then short channel effects are mitigated, but current crowding at the channel-source/drain interface increases
Solution Approach 1:
The patent employs multiple vertical nanosheet channels stacked in the vertical dimension above the gate electrode. This stacking approach increases the total effective channel cross-sectional area available for current flow, distributing the current density across multiple channels and reducing current crowding effects at the channel-source/drain interface while maintaining thin individual channel thicknesses for good gate control.
Solution Approach 2:
The patent divides the channel function across multiple discrete vertical nanosheet channels rather than using a single thick channel. Each nanosheet channel is thin enough for effective gate control, and the collection of stacked channels provides sufficient total conductive area to handle the required current, thereby segmenting the current path to reduce crowding effects.
3Ease of manufacture
If conventional planar transistors are used to simplify manufacturing, then fabrication processes are easier, but integration density and device performance are limited
Solution Approach 1:
The patent employs selective epitaxial growth to pre-form the vertical nanosheet channel structures with precise thickness and composition control before subsequent processing steps. This preliminary formation of the three-dimensional channel architecture enables later manufacturing steps to proceed with conventional lithography and deposition techniques, maintaining ease of manufacture while achieving high integration density through the vertically stacked channel configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved performance by providing lower resistance at the channel-source/drain interface, enhanced On-current, and increased connection margin, while allowing for deep source/drain strain effects and effective control of channel thicknesses.
Implementation Method 1
depositing a first nanosheet over the first sheet, the first nanosheet including a first material and having a first thickness; depositing a second nanosheet over the second sheet, the second nanosheet including the first material and having a second thickness greater than the first thickness
Implementation Method 2
depositing a first nanosheet over the first sheet, the first nanosheet including a first material and having a first thickness; depositing a second nanosheet over the second sheet, the second nanosheet including the first material and having a second thickness greater than the first thickness
Implementation Method 3
patterning the first sheet, the first nanosheet, the second sheet, and the second nanosheet into a fin; removing the first sheet and the second sheet to form a first nanostructure from the first nanosheet and a second nanostructure from the second nanosheet
Data Source
AI summary
Semiconductor devices and their manufacturing methods are disclosed herein, and more particularly to semiconductor devices including a transistor having gate all around (GAA) transistor structures and manufacturing methods thereof. Different thickness in an epi-growth scheme is adopted to create different sheet thicknesses within the same device channel regions for use in manufacturing vertically stacked nano structure (e.g., nanosheet, nanowire, or the like) GAA devices. A GAA device may be formed with a vertical stack of nanostructures in a channel region with a topmost nanostructure of the vertical stack being thicker than the other nanostructures of the vertical stack. Furthermore, an LDD portion of the topmost nano structure may be formed as the thickest of the nanostructures in the vertical stack.