GAA Nanosheet Transistor Cell Layout with Inter-Channel Gate Contact
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Solution Overview
Problem
Conventional finFETs face challenges in scaling to smaller dimensions due to limitations in lateral spacing and fin height, which affect the effective width and power consumption of semiconductor circuits.
Innovation Solution
The semiconductor device incorporates gate-all-around (GAA) field effect transistors with horizontal nanosheet conductive channels, where a gate contact is placed between GAA FETs, spaced maximally from source and drain regions, and can have staggered or centered configurations, allowing for varying channel widths to reduce power consumption and enable dense cell layouts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional finFETs are scaled to smaller dimensions, then device density increases, but lateral spacing between adjacent fins and fin height become insufficient
Solution Approach 1:
The patent transitions from planar fin structures to three-dimensional gate-all-around nanosheet structures. The nanosheets are stacked vertically with gate material completely surrounding each nanosheet on all sides (top, bottom, and lateral surfaces), effectively moving the channel structure into the vertical dimension while maintaining controlled lateral spacing between adjacent nanosheets in the stack.
2Quantity of substance
If fin height is increased to achieve desired effective width, then channel width improves, but device height increases
Solution Approach 1:
The patent divides the channel into multiple discrete horizontal nanosheets stacked vertically. Each nanosheet provides a portion of the total effective channel width, and the gate material completely surrounds each individual nanosheet. This segmentation allows the effective channel width to be controlled by the number and dimensions of individual nanosheets without requiring a proportional increase in overall device height, as each nanosheet is a separate controllable element.
3Area of stationary object
If gate contact is placed closer to source/drain regions, then area is reduced, but spacing requirements are violated
Solution Approach 1:
The gate contact is positioned in the inter-channel spacing region between adjacent GAA FETs, utilizing the vertical and lateral space between channels. By completely surrounding each nanosheet with gate material, the design creates dedicated gate contact regions in the spacing areas, allowing gate contacts to be placed closer to source/drain regions without violating minimum spacing rules, as the gate material provides proper isolation and electrical separation.
Data Source
AI summary
A semiconductor device includes first and second GAA FETs spaced apart by an inter-channel spacing. Each of the GAA FETs includes a horizontal nanosheet conductive channel structure, a gate material completely surrounding the horizontal nanosheet conductive channel structure, source and drain regions at opposite ends of the horizontal nanosheet conductive channel structure, source and drain contacts on the source and drain regions. A width of the horizontal nanosheet conductive channel structure of the first GAA FET or the second GAA FET is smaller than a maximum allowed width. The semiconductor device also includes a gate contact on the gate material in the inter-channel spacing between the first and second GAA FETs. The gate contact is spaced apart by a distance from each of the source and drain regions of the first and second GAA FETs in a range from a minimum design rule spacing to a maximum distance.