GAA Nanosheet Stack Layout With Variable Sheet Counts
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Solution Overview
Problem
The semiconductor industry faces challenges in fabricating Gate-All-Around (GAA) devices as feature sizes and spacing decrease, limiting device flexibility and performance improvements due to the use of a uniform number of nanosheets across the entire chip or wafer, which restricts power, performance, area, and cost (PPAC) gains.
Innovation Solution
The implementation of semiconductor structures with varying numbers and widths of nanosheets across a single chip or wafer, allowing for customizable nanosheet stack configurations to match specific functional blocks' power and speed requirements, thereby improving device performance and manufacturability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a uniform number of nanosheets is used across the entire chip or wafer, then fabrication process simplicity is maintained, but device flexibility and performance optimization are limited
Solution Approach 1:
The fabrication process is segmented into multiple sequential deposition cycles, where each cycle deposits a pair of nanosheet layers. By controlling the number of cycles and selectively removing nanosheets in different regions, the process creates variable nanosheet configurations across the wafer while maintaining a systematic, repeatable fabrication approach.
Solution Approach 2:
The patent implements local quality by enabling different functional blocks on the same wafer to have different numbers of nanosheets (e.g., 2, 4, or 6 nanosheets) tailored to their specific performance requirements. This is achieved through selective removal processes that modify local regions after uniform deposition, allowing each area to have optimized characteristics without redesigning the entire fabrication process.
2Quantity of substance
If feature sizes and spacing are decreased to increase device density, then higher device density is achieved, but fabrication challenges increase
Solution Approach 1:
The patent transitions from two-dimensional planar transistors to three-dimensional Gate-All-Around structures with vertical nanosheet stacks. This dimensional change allows increased device density by utilizing the vertical dimension for multiple nanosheets stacked along the channel, enabling higher density without proportionally increasing fabrication complexity at the same feature size.
Solution Approach 2:
Multiple nanosheets are nested vertically within a compact footprint, with each nanosheet forming a complete gate-all-around structure. This nesting approach allows four or more transistors to be packed into the area previously occupied by one, significantly increasing device density while maintaining manageable fabrication processes through sequential deposition and selective removal.
3Use of energy by moving object
If varying numbers of nanosheets are implemented across different functional blocks, then power and performance optimization is improved, but fabrication process complexity increases
Solution Approach 1:
The fabrication process is made dynamic through conditional steps where nanosheets are selectively removed based on the desired configuration for different functional blocks. The process can adapt between producing 2, 4, or 6 nanosheets in different regions by controlling the number of deposition cycles and selective removal steps, enabling power-efficient customization without requiring entirely different fabrication processes for each configuration.
Data Source
AI summary
Disclosed are semiconductor devices including a substrate, a first transistor formed over a first portion of the substrate, wherein the first transistor comprises a first nanosheet stack including N nanosheets and a second transistor over a second portion of the substrate, wherein the second transistor comprises a second nanosheet stack including M nanosheets, wherein N is different from M in which the first and second nanosheet stacks are formed on first and second substrate regions that are vertically offset from one another.


