Gate-All-Around Nanosheet Vt Tuning Without Added Parasitic Capacitance

The patent applies local quality by creating different dielectric layer configurations in different regions of the device. Specifically, the gate dielectric layer has different thicknesses in different areas, and dipole layers are selectively formed only in certain regions rather than uniformly across the entire device. This allows different threshold voltages to be achieved in different transistor regions without requiring increased inter-sheet spacing across the whole device, thereby avoiding increased parasitic capacitance.

The patent changes physical parameters of the gate dielectric layer, specifically its thickness and composition, to achieve multiple threshold voltages. By varying the dielectric constant and thickness of the gate dielectric layer in different regions, and by selectively forming dipole layers, the patent achieves different threshold voltages without increasing the physical inter-sheet spacing, thus avoiding increased parasitic capacitance.

The patent applies preliminary action by forming the dipole layer during an earlier stage of the manufacturing process, specifically as part of the gate dielectric layer formation sequence. The dipole layer is formed conformally on the gate dielectric layer before final gate electrode deposition, allowing threshold voltage adjustment to be built into the standard manufacturing flow rather than requiring additional post-processing steps.

The patent uses the gate dielectric layer as an intermediary medium to achieve threshold voltage control. Instead of directly modifying the gate electrode or channel, the dipole layer is formed within the gate dielectric structure, which mediates the effect on threshold voltage. This approach integrates threshold voltage control into the existing gate stack formation process, avoiding the need for separate complex manufacturing steps.