GAA Nanostructure Layout With Back-Side Source/Drain Contacts
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Solution Overview
Problem
Existing technologies for fabricating gate-all-around (GAA) devices in integrated circuits have not been entirely satisfactory in all aspects as they struggle with scaling down while maintaining reasonable processing margins.
Innovation Solution
The implementation of semiconductor structures with gate-all-around transistors that include vertically stacked nanostructures, utilizing photolithography and self-aligned processes for patterning, and incorporating back-side source/drain contacts to reduce local interconnection resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If gate-all-around devices are scaled down to reduce chip footprint, then functional density increases, but processing margins deteriorate
Solution Approach 1:
The patent transitions from planar 2D gate structures to three-dimensional gate-all-around structures that completely surround the channel in vertical and lateral dimensions. This dimensional change enables continued scaling by providing superior gate control through 3D geometry rather than relying solely on lateral dimension reduction, thus maintaining processing margins while reducing chip footprint.
Solution Approach 2:
The gate structure is nested around the channel region in a conformal manner, with the gate electrode surrounding the channel on all sides including top, bottom, and lateral surfaces. This nested configuration maximizes the gate's control over the channel while minimizing the space required, enabling density improvement without sacrificing manufacturing precision.
2Ease of manufacture
If conventional fabrication processes are used for GAA devices, then existing manufacturing capabilities are maintained, but performance and efficiency are insufficient
Solution Approach 1:
The fabrication process is divided into distinct sequential stages: forming sacrificial nanostructures, depositing gate dielectric and electrode materials, removing sacrificial structures, and forming source/drain regions. This segmentation allows each step to be optimized independently using existing manufacturing tools while achieving the complex 3D gate-all-around structure required for high performance.
Solution Approach 2:
Sacrificial nanostructures are formed in advance before the gate structure is built. These preliminary structures serve as templates that guide the conformal deposition of gate materials and define the final gate geometry. This preliminary action enables precise 3D gate formation using standard deposition equipment, bridging existing manufacturing capabilities with advanced device performance requirements.
Data Source
AI summary
A semiconductor structure includes a first transistor, a second transistor, a gate structure, and a first source/drain contact. The first transistor includes first nanostructures stacked from each other in a Z-direction, and a first source/drain feature and a second source/drain feature on opposite sides of the first nanostructures in an X-direction. The second transistor is arranged with the first transistor in a Y-direction. The second transistor includes second nanostructures stacked from each other in the Z-direction, and a third source/drain feature and a fourth source/drain feature on opposite sides of the second nanostructures in the X-direction. The gate structure extends in the Y-direction and wraps around the first nanostructures and the second nanostructures. The first source/drain contact extends in the Y-direction and is under and electrically connected to the second source/drain feature and the fourth source/drain feature.