GAA Nanostructure Gate Layout for Bottom Channel Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing GAA FET devices and fabrication methods are not entirely satisfactory due to challenges in controlling current through the channel region, particularly on the bottom side, which affects device performance and increases contact resistance.
Innovation Solution
A method for forming a multi-gate semiconductor structure that includes forming fin structures over a substrate, disposing a dummy gate structure, removing portions of the fin structures to form recesses, and forming nanowires and gate structures within these recesses, which enhances control over the channel region and reduces contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a FinFET structure is used with gate electrode adjacent to three side surfaces of channel region, then device density and performance are improved, but the bottom part of channel region is far from gate electrode resulting in poor gate control and increased short-channel effects
Solution Approach 1:
The patent transitions from a planar FinFET structure to a three-dimensional GAA FET structure where the channel region is positioned vertically and surrounded by the gate electrode on all sides. This dimensional change allows the gate to control the channel from top, bottom, and sides, eliminating the poor control issue at the bottom surface that exists in FinFETs.
Solution Approach 2:
The gate electrode is positioned to surround the channel region completely, with the gate wrapping around the channel from all directions. This nested configuration allows the gate structure to enclose the channel region, providing comprehensive control over current flow through the channel from all sides including the bottom surface.
2Reliability
If existing GAA FET fabrication methods are used, then device structure is formed, but contact resistance remains high and device performance is not optimized
Solution Approach 1:
The method performs preliminary actions by first forming the channel region and then sequentially forming the gate dielectric layer and gate electrode around it. Source and drain regions are formed at specific stages, and contact holes are created with precise depth control to ensure optimal electrical contact while minimizing resistance. This staged approach optimizes device performance while managing fabrication complexity.
Solution Approach 2:
The patent applies different materials and processing conditions to different regions of the device. The gate dielectric layer uses high-k material for improved electrical characteristics, source and drain regions are selectively doped, and contact holes are formed with specific depth control to optimize local electrical properties. This localized optimization reduces contact resistance and enhances overall device performance.
Data Source
AI summary
Semiconductor structures and method for forming the same are provided. The semiconductor structure includes a substrate and nanostructures formed over the substrate and spaced apart from each other in a first direction. The semiconductor structure further includes a gate structure wrapping around the nanostructures and a semiconductor layer attached to the nanostructures in a second direction different from the first direction. The semiconductor structure further includes inner spacers sandwiched between the semiconductor layer and the gate structure in the second direction and a silicide layer formed over the semiconductor layer. In addition, a first portion of the semiconductor layer is sandwiched between the inner spacers and the silicide layer in the second direction.