GAA Nanostructure Layout With Dielectric Wall for Higher On-State Current
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Solution Overview
Problem
The integration of multi-gate devices in semiconductor manufacturing is challenging due to increased complexity, which hinders the advancement of semiconductor ICs in achieving smaller, faster, and more complex electronic devices.
Innovation Solution
The implementation of gate all around (GAA) transistor structures with a dielectric wall between horizontal nanostructures, connected to vertical nanostructures, which increases the effective width of the semiconductor structure, improving on-state current and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate devices are integrated to improve gate control and reduce short-channel effects, then device performance is improved, but fabrication complexity increases
Solution Approach 1:
The channel is segmented into multiple gates (front gate, back gate, and side gates) that wrap around the channel region. This segmentation allows independent control of different channel portions, improving gate control and reducing short-channel effects while maintaining manageable fabrication through modular structure formation
Solution Approach 2:
The multi-gate structure employs a nested configuration where front and back gates are positioned on opposite sides of the channel, with side gates wrapping around the channel from the sides. This nested arrangement maximizes gate-channel coupling within a compact footprint, improving control without proportionally increasing fabrication complexity
2Productivity
If device dimensions are scaled down to improve production efficiency and lower costs, then production efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The invention transitions from planar 2D channel structures to three-dimensional multi-gate configurations where gates wrap around the channel in multiple dimensions. This dimensional change allows continued scaling of the channel footprint while maintaining effective gate control through vertical and lateral gate extensions, thereby improving production efficiency without sacrificing manufacturing precision
Solution Approach 2:
The side gates are configured to wrap around the channel with curved surfaces rather than straight edges, creating a more spherical or cylindrical gate-channel interface. This curvature maximizes the gate-controlled area within minimal lateral space, enabling further device miniaturization while maintaining manufacturing feasibility through standardized curved patterning processes
Data Source
AI summary
Semiconductor structures and methods for forming the same are provided. The semiconductor structure includes a plurality of first horizontal nanostructures formed over a substrate, and a plurality of second horizontal nanostructures adjacent to the first horizontal nanostructures. The semiconductor structure includes a dielectric wall formed between the first horizontal nanostructures and the second horizontal nanostructures. The semiconductor structure also includes a vertical nanostructure between the dielectric wall and the first horizontal nanostructures, and the vertical nanostructure is connected to and in direct contact with the dielectric wall. The semiconductor structure includes a gate structure surrounding the first horizontal nanostructures, the second horizontal nanostructures and the vertical nanostructure.