Gate-All-Around Nanostructure Formation With Dopant-Diffusion Etch Control
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Solution Overview
Problem
The semiconductor industry faces challenges in forming reliable semiconductor devices at increasingly smaller sizes due to the complexity and difficulty of fabrication processes as feature sizes decrease, leading to issues with surface roughness and defect formation during thermal operations.
Innovation Solution
A method involving a thermal operation to diffuse n-type dopants into a semiconductor substrate, followed by the formation of a semiconductor stack with alternating sacrificial and semiconductor layers, which improves etching selectivity and allows for the creation of fin structures and metal gate stacks, enhancing the reliability and performance of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If feature sizes continue to decrease to increase functional density, then production efficiency increases and costs decrease, but fabrication process complexity and difficulty increase
Solution Approach 1:
The fabrication process is divided into multiple sequential stages: forming sacrificial layers, forming semiconductor layers, selective removal of sacrificial layers, and gate formation. This segmentation allows each step to be optimized independently, managing the overall process complexity while enabling continued scaling.
Solution Approach 2:
Sacrificial layers are formed in advance before the semiconductor layers. This preliminary action establishes a framework that guides subsequent processing steps, including where to form gates and how to structure the final device, thereby simplifying the overall fabrication sequence.
2Length of stationary object
If feature sizes continue to decrease, then geometric size decreases, but manufacturing precision and reliability become more difficult to achieve
Solution Approach 1:
Sacrificial layers serve as intermediary structures that define the spatial relationships and dimensions of the final device features. These temporary structures enable precise positioning and sizing of semiconductor layers and gates, achieving high manufacturing precision even at reduced feature sizes.
Solution Approach 2:
The process utilizes changes in material properties and layer thicknesses to control feature dimensions. By adjusting the thickness of sacrificial and semiconductor layers, and controlling etching parameters, precise geometric control is achieved at smaller feature sizes.
3Quantity of substance
If thermal operations are performed during fabrication, then dopant diffusion occurs, but surface roughness and defect formation increase
Solution Approach 1:
Sacrificial layers are designed as temporary, disposable structures that are removed after serving their guiding function. This allows aggressive thermal processing to be performed during fabrication without permanently damaging the final device structure, as the sacrificial layers absorb the thermal stress and can be discarded.
Solution Approach 2:
The sacrificial layers provide a protective buffer during thermal operations, cushioning the semiconductor layers from direct thermal damage. This beforehand cushioning allows necessary dopant diffusion while minimizing surface roughness and defect formation in the permanent structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the etching selectivity and process window, leading to enhanced performance and reliability of semiconductor devices by facilitating the formation of fin structures and metal gate stacks, thus addressing the challenges of smaller feature sizes.
Implementation Method 1
A thermal operation is performed to an n-type doped region in a semiconductor substrate such that some n-type dopants diffuse out of the n-type doped region
Data Source
AI summary
A method for forming a semiconductor device structure is provided. The method includes forming an n-type doped region in a semiconductor substrate and forming a semiconductor stack over the semiconductor substrate. The semiconductor stack has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes introducing n-type dopants from the n-type doped region into the semiconductor stack during the forming of the semiconductor stack. The method further includes patterning the semiconductor stack to form a fin structure and forming a dummy gate stack to wrap around a portion of the fin structure. In addition, the method includes removing the dummy gate stack and the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor layers. The method includes forming a metal gate stack to wrap around the semiconductor nanostructures.