Stacked GAA Nanostructure Layout for Simultaneous Inner Spacer Formation
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Solution Overview
Problem
The integration of gate-all-around (GAA) transistor features around nanowires is challenging due to limitations in current fabrication methods, necessitating continued improvements for enhanced performance.
Innovation Solution
The method involves stacking NFET and PFET between buried power rails, enhancing PFET mobility by increasing Ge concentration in the PFET channel region, and forming inner spacers and nanostructures simultaneously for both NFET and PFET.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If current fabrication methods are used for GAA transistor integration, then existing process compatibility is maintained, but integration challenges and manufacturing complexity increase
Solution Approach 1:
The patent combines the formation of inner spacers and nanowire structures into a single integrated process step. The inner spacer material is deposited conformally around the nanowire, and subsequent etching simultaneously defines both the inner spacer boundaries and the nanowire release patterns, merging two fabrication operations into one unified process sequence.
Solution Approach 2:
The methodology performs preliminary patterning of the inner spacer material before final nanowire release. By pre-forming the inner spacer structure with appropriate material layers and patterns, the subsequent nanowire release and gate formation steps are simplified, as the inner spacer already serves as a predefined template and protection structure.
2Manufacturing precision
If separate formation processes are used for inner spacers and nanowires, then individual structure precision is maintained, but production time and cost increase
Solution Approach 1:
The patent merges the formation of inner spacers and nanowire structures into a single integrated process step. The inner spacer material is deposited conformally around the nanowire, and subsequent etching simultaneously defines both the inner spacer boundaries and the nanowire release patterns, merging two fabrication operations into one unified process sequence.
Solution Approach 2:
The inner spacer material serves multiple functions simultaneously: it acts as a structural component, a release pattern definition, and a guide for subsequent gate formation. This multi-functionality eliminates the need for separate dedicated processes for each function, improving productivity while maintaining precision through the unified approach.
3Reliability
If Ge concentration is increased in PFET channel region, then PFET mobility is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent applies different Ge concentrations to different transistor types within the same integrated circuit. The PFET channel region receives enhanced Ge concentration to improve mobility, while other regions maintain standard compositions. This localized material modification is achieved through selective deposition or in-situ doping processes targeted at specific device regions.
Solution Approach 2:
The methodology modifies the Ge concentration parameter in the semiconductor layers to optimize PFET performance. By adjusting the Ge content in the channel region, the patent enhances carrier mobility and device reliability, demonstrating parameter optimization as a key strategy for improving device characteristics without fundamental process changes.
Data Source
AI summary
A semiconductor device structure includes first nanostructures formed over a substrate. The structure also includes a first gate structure wrapping around the first nanostructures. The structure also includes a first source/drain epitaxial structure formed beside the first nanostructures. The structure also includes a first inner spacer between the first gate structure and the first source/drain epitaxial structure. The structure also includes second nanostructures formed over the first nanostructure. The structure also includes a second gate structure wrapping around the second nanostructures. The structure also includes a second source/drain epitaxial structure formed beside the second nanostructures. The structure also includes a second inner spacer between the second gate structure and the second source/drain epitaxial structure. A sidewall of the second inner spacer is spaced apart from a sidewall of the first inner spacer when viewed from above.