GAA Nanostructure Profiling After Sacrificial Layer Removal
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices continue to integrate more components into a given area through reduced minimum feature sizes, challenges arise in the fabrication of Gate All Around (GAA) transistors, particularly in shaping the nanostructures and removing sacrificial layers efficiently.
Innovation Solution
A method involving the formation of a multilayer stack with semiconductor nanostructures and sacrificial layers, followed by etching processes to shape the nanostructures, including the use of specific etching gases and chemicals to remove intermix layers and form precise nanostructure profiles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional lithography and etching processes are used to reduce minimum feature size for higher integration density, then more components can be integrated into a given area, but the fabrication of GAA transistors becomes increasingly difficult due to challenges in shaping nanostructures and removing sacrificial layers
Solution Approach 1:
The patent divides the GAA transistor fabrication into distinct stages with separate etching processes: first forming the multilayer stack with semiconductor and sacrificial layers, then removing sacrificial layers to create voids, and finally forming gate structures around the semiconductor nanostructures. This segmentation allows each step to be optimized independently, addressing the fabrication difficulty while maintaining high integration density.
Solution Approach 2:
The patent performs preliminary actions by first forming the complete multilayer stack with alternating semiconductor and sacrificial layers before removing the sacrificial layers. This preliminary structuring enables subsequent self-aligned gate formation and simplifies the overall fabrication process, making it easier to manufacture high-density GAA transistors.
2Manufacturing precision
If etching processes are used to shape nanostructures in GAA transistors, then precise control over nanostructure profiles is achieved, but the complexity of the fabrication process increases
Solution Approach 1:
The patent applies local quality by using selective etching processes that target specific materials at specific locations. The first etching process selectively removes sacrificial layers while preserving semiconductor layers, and the second etching process shapes the semiconductor nanostructures. This localized selective etching achieves precise nanostructure profile control while managing fabrication complexity through material-specific process optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the efficient fabrication of GAA transistors with improved performance by shaping the nanostructures and ensuring precise control over the nanostructure profiles, enhancing integration density and device performance.
Implementation Method 1
An etching process may then be performed to remove the germanium intermix layers on the surfaces of the semiconductor nanostructures. The profile of the nanostructures is also shaped through the etching process.
Data Source
AI summary
A method includes forming a multilayer stack, which includes a plurality of semiconductor layers and a plurality of sacrificial layers located alternatingly. The method further includes forming a dummy gate stack on the multilayer stack, etching the multilayer stack to form a trench, epitaxially growing a semiconductor region in the trench to form a source/drain region, and removing the plurality of sacrificial layers from the multilayer stack. After the sacrificial layers are removed, an etching process is performed. After the etching process, a gate stack is formed around the plurality of semiconductor layers.