GAA Nanostructure Enlargement for Low-Resistance Source/Drain Contact
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Solution Overview
Problem
As semiconductor devices continue to shrink in size, challenges arise in efficiently forming source and drain regions with fewer defects, higher current flow, and reduced resistance, particularly in nanostructure field-effect transistors, due to imperfect precision in lateral etching processes that can remove critical channel region portions.
Innovation Solution
The formation of inner spacers between channel regions is enhanced by creating a layer of semiconductor material over recesses formed by lateral etching, followed by an inner spacer layer, and etching both to form distinct inner spacers that are substantially level with the semiconductor material, providing greater surface area for epitaxial growth of source and drain regions, thereby improving current flow and reducing resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If lateral etching is used to form recesses in fins, then source and drain regions can be formed, but critical portions of the channel region are removed due to imperfect precision
Solution Approach 1:
A layer of semiconductor material is formed over the etched side portions before the inner spacer layer is deposited. This preliminary action ensures that even if lateral etching removes critical channel portions, the semiconductor material layer can restore the channel region, preventing loss of active channel area while still allowing source and drain region formation.
Solution Approach 2:
The inner spacer structure is designed with specific dimensions and positioning to provide a protective buffer zone. The inner spacer extends into the recesses and provides mechanical support and protection to the channel region during subsequent processing steps, cushioning against further damage from imperfect etching precision.
2Productivity
If conventional fabrication processes are used, then device integration is achieved, but defect formation increases and current flow decreases at scaled dimensions
Solution Approach 1:
The fabrication process is segmented into distinct stages: forming recesses, depositing semiconductor material layer, depositing inner spacer layer, and etching to form inner spacers. This segmentation allows each step to be optimized independently, ensuring high-quality source and drain regions while maintaining high integration density through precise control of each process stage.
Solution Approach 2:
The invention changes critical process parameters including the thickness of the semiconductor material layer, the composition and thickness of the inner spacer layer, and the etching conditions. These parameter changes enable the formation of high-quality source and drain regions with fewer defects, improving reliability while maintaining productivity through efficient process integration.
3Area of stationary object
If feature sizes are reduced to increase integration density, then more components fit in given area, but additional problems arise in forming source and drain regions
Solution Approach 1:
The inner spacer is nested within the recesses formed in the fins, and the semiconductor material layer is nested over the etched side portions. This nested structure allows the source and drain regions to be formed precisely within the confined spaces of scaled-down devices, enabling high integration density while managing the complexity of forming source and drain regions at small dimensions through self-aligned processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in more uniform and defect-free source and drain regions with increased surface area, facilitating faster and more robust epitaxial growth, enhancing current flow and minimizing resistance, leading to a saturation current gain of about 5% to 10% in nano-FETs.
Implementation Method 1
facilitating faster and more robust epitaxial growth
Data Source
AI summary
A method of forming a semiconductor device includes forming a fin of alternating layers of semiconductor nanostructures and sacrificial layers, laterally etching sidewall portions of the sacrificial layers, and depositing additional semiconductor material over the sidewalls of the semiconductor nanostructures and sacrificial layers. Following deposition of a dielectric material over the additional semiconductor material and additional etching, the remaining portions of the semiconductor structures and additional semiconductor material collectively form a hammer shape at each opposing side of the fin. Epitaxial source/drain regions formed on the opposing sides of the fin will contact the heads of the hammer shapes.