GAA Nanowire Device With Vertical Stack And Shared Gate
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Solution Overview
Problem
There is a need for a more compact and dense gate-all-around (GAA) nanowire semiconductor device that can efficiently scale to advanced technology nodes while maintaining superior electrostatic control and reducing threshold voltage variation, as FinFET devices face challenges with parasitic capacitances and resistances at smaller technology nodes.
Innovation Solution
A nanowire semiconductor device with a vertical stack of nanowires comprising different materials, where the second-type nanowires have outer parts made of a different material than the inner part, allowing for a shared gate structure around both types of nanowires, enabling compact design and higher mobility through the integration of Si and SiGe materials, and eliminating the need for additional doping in the channel region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If FinFET devices are used to increase chip density, then device density is improved, but parasitic capacitances and resistances worsen at advanced technology nodes
Solution Approach 1:
The patent transitions from planar FinFET architecture to a vertically-stacked nanowire architecture, moving the device structure into the third dimension. Multiple nanowires are stacked vertically with a shared gate, enabling continued scaling and density improvement while maintaining electrostatic control and reducing parasitic effects through the gate-all-around configuration.
Solution Approach 2:
The patent employs different semiconductor materials for different nanowires in the stack (e.g., Si, SiGe, III-V materials) to optimize device performance. High-mobility materials are used for channels requiring faster carrier transport, while other materials are used for their complementary properties, allowing simultaneous optimization of drive current and threshold voltage control.
2Productivity
If channel length is scaled down to increase device density, then device density is improved, but electrostatic control deteriorates
Solution Approach 1:
By stacking nanowires vertically and wrapping the gate around all surfaces of each nanowire, the patent achieves superior electrostatic control in the short-channel regime. The gate-all-around configuration provides three-dimensional control over the channel, effectively suppressing short-channel effects even as channel length is reduced to increase density.
3Ease of operation
If doped channel is used to adjust threshold voltage, then threshold voltage control is improved, but threshold voltage variation between devices increases
Solution Approach 1:
The patent applies doping selectively to specific regions of the nanowire structure - the source and drain regions are doped while the channel region remains undoped or lightly doped. This local differentiation allows threshold voltage control through material selection and geometric configuration rather than uniform channel doping, reducing device-to-device variation.
4Adaptability or versatility
If separate stacks are used for nFET and pFET to manufacture devices, then device functionality is improved, but device complexity increases
Solution Approach 1:
The patent integrates both n-type and p-type nanowire transistors within a single shared stack structure. Different nanowires in the same stack can be configured with different materials and doping to form either nFET or pFET devices, sharing common gates and reducing overall device complexity while maintaining full functionality.
Data Source
AI summary
The disclosed technology generally relates to a semiconductor device, and more particularly to a gate all around (GAA) semiconductor device and a method for fabricating the same. In one aspect, a semiconductor device has a vertical stack of nanowires formed on a substrate, wherein the vertical stack of nanowires comprises an n-type nanowire and a p-type nanowire each extending in a longitudinal direction parallel to a main surface of the substrate. The n-type nanowire comprises a first material and the p-type nanowire comprises an inner part having two sides and an outer part at each side of the inner part in the longitudinal direction, wherein one or both of the two outer parts comprises a second material different from the first material. The n-type nanowire and the p-type nanowire each comprises a channel region electrically coupled to respective source and drain regions. The channel region of the p-type nanowire comprises the inner part. The device additionally includes a shared gate structure circumferentially surrounding the channel regions of the n-type and p-type nanowires.