Gate-All-Around Nanowire Structure With Dopant Diffusion Blocking
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in scaling multi-gate and nanowire transistors below the 10 nanometer node, where conventional fabrication processes face limitations in patterned feature dimensions and spacing, leading to issues like dopant diffusion and enhanced leakage between source and drain, which affect transistor performance.
Innovation Solution
Implementing a dopant diffusion blocking layer, such as carbon-doped silicon or silicon germanium, beneath the channel region to prevent unwanted dopant diffusion and enhance leakage, combined with a self-aligned gate endcap architecture to improve transistor performance and enable scaling to future technology nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional fabrication processes are used for scaling multi-gate and nanowire transistors below 10 nanometer node, then manufacturing simplicity is maintained, but dopant diffusion and leakage between source and drain increase, degrading transistor performance
Solution Approach 1:
A sacrificial nanowire layer is introduced as an intermediary structure between the source and drain regions. This sacrificial layer prevents direct dopant diffusion between source and drain during fabrication, eliminating the harmful leakage path while maintaining manufacturing feasibility. The sacrificial nanowire is later removed to complete the gate-all-around structure.
Solution Approach 2:
The sacrificial nanowire layer is formed in advance before source and drain doping occurs. This preliminary structure establishes a physical barrier that prevents dopant diffusion during subsequent processing steps, addressing the reliability issue before the harmful diffusion can occur.
2Productivity
If feature dimensions are reduced to increase device density, then capacity increases, but lithographic constraints and manufacturing precision requirements become overwhelming
Solution Approach 1:
The invention transitions from planar patterning to three-dimensional self-aligned structures. By forming sacrificial nanowires and using them as templates for gate formation, the process eliminates the need for extremely precise lithographic patterning at sub-10nm nodes, as the critical dimensions are defined by deposition and etching processes rather than lithography.
Solution Approach 2:
The sacrificial nanowire structure serves multiple functions: it defines the channel position, guides gate formation, and prevents dopant diffusion. The structure is self-aligned through the fabrication process, eliminating the need for separate alignment steps and reducing manufacturing precision requirements.
3Reliability
If gate-all-around structures are implemented to improve short channel control, then transistor performance improves, but fabrication process complexity increases
Solution Approach 1:
The sacrificial nanowire acts as a mediator that simplifies the formation of complex gate-all-around structures. By using the sacrificial layer as a template, the gate can be deposited conformally around the nanowire, automatically creating the three-dimensional gate structure without complex lithographic patterning or multiple deposition steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively prevents dopant diffusion and enhances transistor performance, enabling the scaling of gate-all-around technologies to future nodes with improved short channel control and reduced leakage, applicable to various channel materials and architectures.
Implementation Method 1
a fin including a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer
Data Source
AI summary
Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin. The fin includes a dopant diffusion blocking layer on a first semiconductor layer, and a second semiconductor layer on the dopant diffusion blocking layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.