GAA Nanowire Layout With Disjoined Epitaxial Source-Drain Regions
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in maintaining mobility and short channel control as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, where there is a trade-off between feature size and spacing, leading to undesirable merging of epitaxial source or drain structures in high-density locations without self-aligned gate endcap (SAGE) walls.
Innovation Solution
The method involves fabricating neighboring gate-all-around integrated circuit structures with disjoined epitaxial source or drain regions using a high temperature carbon hardmask and lithographic patterning to split merged epitaxial regions, followed by dielectric backfilling and etching to create isolated structures, enabling more aggressive diffusion spacing and robust functionality in next-generation transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature size is scaled down to increase device density, then the number of functional units per chip area increases, but the spacing between features becomes too small causing manufacturing precision issues
Solution Approach 1:
The patent segments the continuous epitaxial region into discrete, separated regions using patterned sacrificial nanowires. This segmentation allows each epitaxial region to be independently formed and controlled, preventing unwanted merging while maintaining high device density. The sacrificial nanowires act as physical dividers that create distinct epitaxial growth zones.
Solution Approach 2:
The patent introduces sacrificial nanowires as intermediary structures during the fabrication process. These nanowires temporarily occupy the space between adjacent device regions, serving as mediators that prevent direct contact and merging of epitaxial regions. After epitaxial growth, the sacrificial nanowires are removed, leaving clean separations between the now-discrete epitaxial regions.
2Reliability
If multi-gate and nanowire transistors are fabricated to improve short channel control, then device performance improves, but lithographic process constraints become overwhelming
Solution Approach 1:
The patent performs preliminary actions by forming sacrificial nanowire patterns and epitaxial regions before final device assembly. The sacrificial nanowires are deposited and patterned early in the process, establishing the framework for subsequent epitaxial growth. This preliminary structuring simplifies later lithographic steps by pre-defining critical feature locations and separations.
Solution Approach 2:
The patent transitions from two-dimensional lithographic patterning to three-dimensional structure formation using vertically-oriented sacrificial nanowires and epitaxial growth. By utilizing the vertical dimension for sacrificial nanowire placement and epitaxial region formation, the process bypasses some of the limitations of planar lithography, enabling finer feature control without proportionally increasing lithographic complexity.
3Ease of manufacture
If epitaxial regions are allowed to merge in high-density locations, then manufacturing process simplifies, but undesirable merging occurs compromising device performance
Solution Approach 1:
The patent applies preliminary anti-action by introducing sacrificial nanowires that actively prevent the merging of epitaxial regions before it can occur. These nanowires are positioned in advance to counteract the natural tendency of epitaxial material to spread and merge during growth. The sacrificial structures create physical barriers that maintain the desired separation between epitaxial regions throughout the growth process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for higher layout density and improved performance by preventing unwanted merging of epitaxial growth, enhancing diffusion spacing, and enabling the integration of multi-width nanowires and nanoribbons in both SAGE and non-SAGE architectures, thus addressing the limitations of conventional lithographic processes.
Implementation Method 1
performing an etch process to split merged epitaxial regions
Implementation Method 2
backfilling with dielectric material
Data Source
AI summary
Neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, and methods of fabricating neighboring gate-all-around integrated circuit structures having disjoined epitaxial source or drain regions, are described. For example, a structure includes first and second vertical arrangements of nanowires, the nanowires of the second vertical arrangement of nanowires having a horizontal width greater than a horizontal width of the nanowires of the first vertical arrangement of nanowires. First and second gate stacks are over the first and second vertical arrangements of nanowires, respectively. First epitaxial source or drain structures are at ends of the first vertical arrangement of nanowires, and second epitaxial source or drain structures are at ends of the second vertical arrangement of nanowires. An intervening dielectric structure is between neighboring ones of the first epitaxial source or drain structures and of the second epitaxial source or drain structures.