Gate-All-Around Nanowire Structure With Alternate Etch-Selective Material
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in achieving precise etch selectivity between Si and SiGe materials, which is crucial for nanowire and nanoribbon transistor architectures, as inter-diffusion renders etch selectivity less effective, leading to thinner-than-planned nanowires and increased leakage/shorting issues.
Innovation Solution
The introduction of an alternate etch selective material (ESM) replaces SiGe post-fin patterning, allowing for higher etch selectivity and control by selectively etching SiGe using clamping pillars, followed by filling the spaces with a material exhibiting high dimple etch selectivity, thereby reducing material exposure and variations in etch rate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SiGe sacrificial material is used for nanowire fabrication, then the fabrication process can proceed with conventional materials, but etch selectivity is reduced due to inter-diffusion leading to thinner-than-planned nanowires and increased leakage/shorting issues
Solution Approach 1:
The patent changes the material parameter of the sacrificial layer from SiGe to metal oxide (such as Al2O3, TiO2, or Ta2O5), which exhibits fundamentally different etch selectivity characteristics. This material substitution resolves the inter-diffusion problem by providing a sacrificial layer that can be selectively removed without compromising nanowire thickness control or introducing leakage paths.
2Productivity
If feature dimensions are scaled down to increase device density, then capacity increases, but lithographic process constraints become overwhelming with trade-offs between critical dimension and spacing
Solution Approach 1:
The patent transitions from planar 2D patterning constraints to 3D vertical structures by forming nanowires that extend through the substrate depth. This dimensional change allows increased device density through vertical stacking while the metal oxide sacrificial layer enables precise control of nanowire dimensions through selective etching processes that are less constrained by lithographic resolution limits.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise dimple etch control and reduced nanowire/nanoribbon loss, improving channel-to-gate leakage and overlap capacitance, and allows for more aggressive scaling of transistor dimensions without compromising performance.
Implementation Method 1
The introduction of an alternate etch selective material (ESM) replaces SiGe post-fin patterning, allowing for higher etch selectivity and control by selectively etching SiGe using clamping pillars
Implementation Method 2
filling the spaces with a material exhibiting high dimple etch selectivity
Data Source
AI summary
Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.