Gate-All-Around Nanowire Structure With Alternate Etch-Selective Material
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in integrated circuit fabrication lies in achieving precise etch selectivity between Si and SiGe materials, which is crucial for nanowire and nanoribbon transistor architectures, as inter-diffusion renders etch selectivity less effective, leading to thinner-than-planned nanowires and increased leakage/shorting issues.
Innovation Solution
The introduction of an alternate etch selective material (ESM) replaces SiGe early in the process flow, allowing for higher etch selectivity and control by selectively etching SiGe using clamping pillars, followed by filling the spaces with a material exhibiting high dimple etch selectivity, thereby reducing variations in etch rate and minimizing exposed materials during the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If SiGe material is used as sacrificial layer for nanowire release, then nanowire structure can be formed, but etch selectivity between Si and SiGe degrades due to inter-diffusion, leading to thinner nanowires and increased leakage
Solution Approach 1:
The patent applies preliminary action by forming a protective cap layer over the nanowire structure before the release etch process. This cap layer prevents premature etching and maintains nanowire integrity until the precise moment of release, thereby preserving manufacturing precision and preventing leakage issues that would result from premature or uncontrolled etching
Solution Approach 2:
The patent introduces an intermediary material (such as silicon nitride or silicon oxide) that serves as a mediator between the SiGe sacrificial layer and the etch process. This intermediary layer provides the necessary etch selectivity barrier, preventing direct inter-diffusion between Si and SiGe while still allowing controlled release when needed, thus maintaining both nanowire thickness control and leakage prevention
2Manufacturing precision
If conventional etch process is used on SiGe, then nanowire release can be achieved, but etch rate variations increase and dimple shape precision deteriorates
Solution Approach 1:
The patent applies local quality by creating a non-uniform protective structure where the cap layer thickness or composition varies in different regions. This local variation allows precise control over where and how the dimple forms during etching, ensuring high dimple shape precision while maintaining consistent overall etch rates across the wafer
Solution Approach 2:
The patent employs parameter changes by adjusting etch process conditions such as temperature, pressure, or chemistry composition to optimize the etch rate for the specific sacrificial layer material. These parameter adjustments ensure consistent etch rates while achieving the precise dimple shapes required for high-quality nanowire release
3Productivity
If feature size is scaled down to increase device density, then more devices fit on chip, but lithographic patterning constraints become overwhelming, especially regarding critical dimension vs spacing trade-off
Solution Approach 1:
The patent applies dimensionality change by transitioning from planar 2D patterning to 3D vertical structures. By forming nanowires and multi-layered sacrificial layer stacks, the design moves critical dimensions into the vertical dimension where lithographic constraints are less severe, enabling higher device density while maintaining patterning precision through self-aligned vertical formation processes
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise dimple etch and nanowire/nanoribbon release, reducing nanowire/nanoribbon loss and achieving a precise dimple shape, leading to improved channel-to-gate leakage control and overlap capacitance, thus enhancing the performance and reliability of gate-all-around integrated circuit structures.
Implementation Method 1
selectively etching SiGe using clamping pillars, followed by filling the spaces with a material exhibiting high dimple etch selectivity
Data Source
AI summary
Gate-all-around integrated circuit structures fabricated using alternate etch selective material, and the resulting structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is over the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is along sides of the gate stack and over the vertical arrangement of horizontal nanowires. A metal oxide material is between adjacent ones of the vertical arrangement of horizontal nanowires at a location between the pair of dielectric spacers and the sides of the gate stack.