Differentiated Internal Spacers in GAA Nanowire Transistors
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Solution Overview
Problem
The challenge in fabricating multi-gate transistors, such as tri-gate transistors, lies in maintaining mobility improvement and short channel control as device dimensions scale below the 10 nanometer node, particularly in nanowire and nanoribbon architectures, where lithographic processes face constraints due to the trade-off between feature dimension and spacing, and it is difficult to independently tune the performance of NMOS and PMOS transistors.
Innovation Solution
Implementing a carbon hardmask recess and PVD protective liner scheme to de-couple the internal spacer fabrication for the top and bottom parts of nanoribbon stacks, along with self-aligned bottom-up oxidation for nanowire transistor channel depopulation and sub-fin isolation, allowing for separate tuning of n and p MOS performance and varying the number of active nanowire or nanoribbon channels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithographic processes are used to pattern nanowire transistors, then feature dimensions can be reduced, but spacing between features becomes insufficient and manufacturing precision deteriorates
Solution Approach 1:
The patent segments the internal spacer fabrication into two independent parts: first internal spacers formed at a first location and second internal spacers formed at a second location. This segmentation allows each spacer to be independently patterned and tuned, eliminating the need for aggressive lithographic patterning while maintaining sufficient spacing between features.
Solution Approach 2:
The patent applies local quality by enabling independent tuning of the first and second internal spacers with different lengths, materials, or compositions. This allows differentiated performance characteristics for NMOS and PMOS transistors located at different positions, resolving the spacing constraint by providing local customization rather than uniform patterning.
2Ease of manufacture
If multi-gate transistors are fabricated on bulk silicon substrates, then manufacturing cost is reduced and fabrication process is simplified, but mobility improvement and short channel control deteriorate at dimensions below 10nm
Solution Approach 1:
The patent transitions from planar 2D patterning to 3D vertical structures by forming gate-all-around nanowire transistors with internal spacers extending in multiple dimensions. This dimensional change enables superior short channel control through enhanced gate control in the vertical direction while maintaining compatibility with bulk silicon substrates and conventional fabrication processes.
3Length of moving object
If internal spacers are formed using conventional lithographic patterning, then feature dimensions are reduced, but the ability to independently tune NMOS and PMOS performance deteriorates
Solution Approach 1:
The patent segments the internal spacer structure into first internal spacers and second internal spacers that can be independently formed, sized, and material-selected. This segmentation restores independent tuning capability for NMOS and PMOS devices, allowing each transistor type to be optimized separately without being constrained by uniform lithographic patterning requirements.
Solution Approach 2:
The patent employs preliminary actions by forming sacrificial structures and using selective epitaxial growth or deposition to create the first and second internal spacers before final transistor fabrication. This preliminary structuring enables subsequent independent tuning of spacer parameters without requiring aggressive lithographic steps, preserving adaptability while achieving precise dimensional control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables fine-tuning of internal spacer length, channel length, and material composition for both NMOS and PMOS, achieving differentiated performance and reducing the need for aggressive lithographic patterning, while facilitating front-to-back via fabrication without damaging surrounding materials.
Implementation Method 1
PVD protective liner scheme
Implementation Method 2
self-aligned bottom-up oxidation for nanowire transistor channel depopulation and sub-fin isolation
Data Source
AI summary
Gate-all-around integrated circuit structures having differentiated internal spacers are described. For example, an integrated circuit structure includes a first set of horizontal nanowires above a sub-fin structure. A first gate structure is over the first set of horizontal nanowires. The first set of horizontal nanowires extends laterally beyond the first gate structure. First dielectric spacers are adjacent to the first gate structure and vertically between adjacent ones of the first set of horizontal nanowires. A second set of horizontal nanowires is over the first set of horizontal nanowires. A second gate structure is over the second set of horizontal nanowires. The second set of horizontal nanowires extends laterally beyond the second gate structure. Second dielectric spacers are adjacent to the second gate structure and vertically between adjacent ones of the second set of horizontal nanowires. The second dielectric spacers are in contact with but discontinuous from the first dielectric spacers.