Regrown Source-Drain Structures in GAA Nanowires for Channel Strain
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, is exacerbated by the constraints on lithographic processes used to pattern features, leading to a trade-off between critical dimension and spacing.
Innovation Solution
Implementing anisotropic etch and regrowth of epitaxial source or drain structures in gate-all-around transistors, creating a continuous surface for better epi growth and enhancing channel strain, along with back-side reveal techniques for front-side fabrication to improve device performance and reduce manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are scaled below the 10 nanometer node to increase density, then capacity increases, but maintaining mobility improvement and short channel control becomes increasingly difficult
Solution Approach 1:
The patent transitions from planar transistor structures to three-dimensional gate-all-around structures where the gate electrode completely surrounds the channel in all directions (top, bottom, and sidewalls). This dimensional change provides enhanced electrostatic control over the channel, effectively suppressing short channel effects even at sub-10nm scale while maintaining high device density
2Ease of manufacture
If multi-gate transistors are fabricated on bulk silicon substrates to reduce cost and simplify process, then manufacturing cost decreases, but mobility improvement is compromised
Solution Approach 1:
The patent introduces strained semiconductor layers (such as silicon germanium) specifically in the source and drain regions adjacent to the channel, while keeping the gate-all-around structure unsubstituted. This localized strain engineering enhances carrier mobility in the critical transport regions without complicating the overall fabrication process or requiring substitution of the gate structure
Solution Approach 2:
The patent employs composite material structures combining different semiconductor materials (e.g., silicon channel with silicon germanium strain layers) to achieve both high carrier mobility and effective short channel control. The gate-all-around structure may be formed from one material while strained regions use different materials, creating a composite device that optimizes both performance and manufacturability
3Reliability
If nanowires are used to fabricate devices to improve short channel control, then short channel control improves, but lithographic process constraints become overwhelming
Solution Approach 1:
The patent forms the gate-all-around structure and defines the channel geometry before introducing the strained source and drain regions. By establishing the gate structure first, the subsequent strain layer deposition and lithographic patterning steps become more manageable, as the gate structure serves as a reference for aligning and positioning the strained regions, thereby reducing overall lithographic process constraints
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances channel strain and device performance while reducing patterning complexity and costs, enabling robust functionality of scaled nanowire transistors with low power and high performance.
Implementation Method 1
regrowth of epitaxial source or drain structures in gate-all-around transistors, creating a continuous surface for better epi growth
Data Source
AI summary
Gate-all-around integrated circuit structures having source or drain structures with regrown central portions, and methods of fabricating gate-all-around integrated circuit structures having source or drain structures with regrown central portions, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. A gate stack is over the vertical arrangements of nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of nanowires. A second epitaxial source or drain structure is at a second end of the vertical arrangement of nanowires. One or both of the first or second epitaxial source or drain structures has a central portion within an outer portion, and an interface between the central portion and the outer portion.