Gate-All-Around Nanowire Structure With Vertically Discrete Source/Drain
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic device fabrication as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, is exacerbated by the trade-off between critical dimension and spacing constraints in lithographic processes.
Innovation Solution
The implementation of gate-all-around integrated circuit structures with vertically discrete source or drain structures, utilizing partial epitaxial deposition and sacrificial material filling, followed by conductive contact formation, to reduce resistance and enable high-performance nanowire transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional lithographic processes are used to pattern transistor features, then manufacturing simplicity is maintained, but the smallest feature dimension and spacing between features cannot be sufficiently reduced for scaling below 10 nanometer node
Solution Approach 1:
The transistor structure is segmented into multiple vertical fins extending from the substrate, with each fin acting as an independent channel region. This segmentation allows the horizontal feature size to be reduced while maintaining functional channel length through the vertical dimension, effectively decoupling the lithographic patterning limit from the electrical channel dimensions.
Solution Approach 2:
The invention transitions from planar 2D transistor channels to 3D vertical fin structures. By extending the channel region vertically into multiple fins, the effective channel length and width are increased without requiring proportional reduction in the lithographic patterning dimensions, enabling scaling below the 10 nanometer node while managing lithographic process complexity.
2Productivity
If device dimensions are reduced to scale below 10 nanometer node, then increased device density is achieved, but maintaining mobility improvement and short channel control becomes challenging
Solution Approach 1:
By creating vertical fin structures, the channel extends into the third dimension, increasing the effective channel width without proportionally reducing the channel length. This dimensional transition improves device density while maintaining the channel length-to-width ratio necessary for short channel control, as the vertical fins provide extended gate control over the channel region.
Solution Approach 2:
The gate structure completely surrounds each vertical fin channel in a nested configuration, with the gate wrapping around the channel from top, bottom, and sidewalls. This gate-all-around structure provides enhanced electrostatic control over the channel, improving short channel control by suppressing leakage currents while maintaining high device density through the vertical fin architecture.
3Ease of manufacture
If multi-gate transistors are fabricated on bulk silicon substrates, then lower cost and simplified fabrication process are achieved, but device performance and short channel control are compromised compared to nanowire structures
Solution Approach 1:
The bulk silicon substrate is segmented into multiple vertical fin structures through selective etching, creating isolated channel regions that resemble nanowire geometries. This segmentation provides improved gate control and device performance characteristics while maintaining compatibility with bulk silicon fabrication processes, avoiding the need for complex nanowire growth techniques.
Solution Approach 2:
Instead of fully removing substrate material to create suspended nanowires, the invention uses partial etching to form fins that extend upward from the substrate surface. This partial action achieves the beneficial nanowire-like electrostatic control and device performance while retaining substrate support for mechanical stability and simplified fabrication, avoiding excessive material removal.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances device performance by reducing resistance and enabling robust functionality with improved interconnect pitch, lower patterning costs, and scalability to 7 nm and below technology nodes.
Implementation Method 1
partial epitaxial source or drain deposition
Data Source
AI summary
Gate-all-around integrated circuit structures having vertically discrete source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having vertically discrete source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the first epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires. A second epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, the second epitaxial source or drain structure including vertically discrete portions aligned with the vertical arrangement of horizontal nanowires.