Gate-All-Around Nanowire Transistors With Strained Source Drain
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Solution Overview
Problem
In the fabrication of gate-all-around integrated circuit structures, maintaining strain in source or drain structures while minimizing parasitic leakage and capacitance is challenging, especially as device dimensions scale below the 10 nanometer node, due to the complexity of sub-fin isolation processes and the need for different metal gates for NMOS and PMOS transistors.
Innovation Solution
The implementation of epitaxial source or drain structures grown pseudomorphically from the underlying substrate, with an ultrathin etch stop layer selectively etched to create a gap between the source or drain and the substrate, and a high-k dielectric layer deposited to isolate and strain the nanowire or nanoribbon channel, reducing leakage and maintaining channel strain.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional tri-gate fabrication processes are used on bulk silicon substrates, then manufacturing cost is reduced and process complexity is simplified, but parasitic leakage and capacitance increase at sub-10nm dimensions
Solution Approach 1:
The substrate interaction is segmented by introducing an insulator layer between the bulk silicon substrate and the active device region. This segmentation electrically isolates the channel from the substrate, eliminating parasitic leakage paths while maintaining the simplicity of bulk silicon processing.
Solution Approach 2:
An insulator layer is introduced as an intermediary between the bulk silicon substrate and the nanowire/nanoribbon channel. This intermediary layer blocks parasitic leakage and capacitance while allowing the device to retain the manufacturing advantages of bulk silicon substrates.
2Productivity
If device dimensions are scaled below 10 nanometer node, then device density and capacity are increased, but maintaining mobility improvement and short channel control becomes more difficult
Solution Approach 1:
The invention transitions from planar 2D channel structures to three-dimensional nanowire or nanoribbon channels with gate-all-around configuration. This dimensional change provides superior electrostatic control and short channel effect suppression at sub-10nm nodes while enabling higher device density.
Solution Approach 2:
The device employs composite material structures including nanowire/nanoribbon channels, high-k dielectric gate insulators, and metal gate electrodes. This composite approach enables simultaneous achievement of high density, mobility improvement, and short channel control at sub-10nm dimensions.
3Strength
If epitaxial source or drain structures are grown pseudomorphically from the substrate, then channel strain is maintained, but parasitic leakage paths may form through the substrate interface
Solution Approach 1:
The harmful substrate interface is extracted or removed from the device structure by introducing an insulator layer. This eliminates parasitic leakage paths while preserving the beneficial strain in the epitaxial source/drain structures through the nanowire/nanoribbon channel.
Solution Approach 2:
An insulator layer is positioned as an intermediary between the epitaxial source/drain structures and the substrate. This intermediary maintains the strain benefit from pseudomorphic growth while blocking parasitic leakage paths through the substrate interface.
4Object-affected harmful factors
If complex sub-fin doping schemes are implemented to reduce parasitic leakage, then leakage control is improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The complex sub-fin doping scheme is replaced by extracting the substrate interface from the active device region through insulator layer introduction. This physical isolation eliminates parasitic leakage paths without requiring complex doping processes, significantly simplifying manufacturing.
Solution Approach 2:
An insulator layer serves as an intermediary that provides parasitic leakage control without requiring complex doping schemes. This intermediary approach achieves leakage reduction through physical isolation rather than chemical modification, reducing device complexity and manufacturing difficulty.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables high-performance nanowire or nanoribbon transistors with minimal parasitic leakage and capacitance, maintaining strain in the channel while simplifying the integration process and eliminating the need for complex sub-fin doping schemes.
Implementation Method 1
a gate dielectric layer of high-k dielectric material is formed over a lowermost portion of the gate stack
Implementation Method 2
epitaxial source or drain structures grown pseudomorphically from the underlying substrate
Data Source
AI summary
Gate-all-around integrated circuit structures having strained source or drain structures on a gate dielectric layer, and methods of fabricating gate-all-around integrated circuit structures having strained source or drain structures on a gate dielectric layer, are described. For example, an integrated circuit structure includes an insulator layer above a substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator layer. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and on the insulator layer. A gate stack is surrounding a channel region of the vertical arrangement of horizontal semiconductor nanowires. The gate stack includes a high-k dielectric layer continuous with and having a same composition as the insulator layer.