Gate-All-Around Nanowire Structure Without Subfin Isolation
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Solution Overview
Problem
The scaling of multi-gate transistors in integrated circuits below the 10 nanometer node poses challenges in maintaining mobility and short channel control, particularly due to the trade-off between feature dimension and spacing, and the complexity of subfin isolation schemes required to prevent source-to-drain leakage.
Innovation Solution
The implementation of gate-all-around integrated circuit structures with an insulator fin on an insulator substrate, which eliminates the need for subfin isolation by using a bottom-seeded epitaxial region and selective depopulation of the substrate beneath the channel, allowing for high channel strain and reduced leakage without the complexity of subfin doping.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multi-gate transistors are scaled below 10 nanometer node, then device density is improved, but maintaining mobility and short channel control becomes difficult
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanowire channels with gate-all-around configuration. This dimensional change enables the gate to control the channel from all directions (top, bottom, and sidewalls), providing superior electrostatic control and short channel effect suppression at sub-10nm nodes while maintaining high device density through vertical stacking of multiple nanowires.
Solution Approach 2:
The patent employs composite material structures including semiconductor nanowires (e.g., Si, SiGe, III-V materials) combined with high-k dielectric gate materials and metal gate electrodes. This composite approach enables optimization of carrier mobility in the nanowire channel while the high-k gate material provides enhanced gate control with reduced leakage, addressing both density and reliability requirements.
2Productivity
If feature dimension is reduced to increase device density, then productivity is improved, but spacing between features becomes constrained
Solution Approach 1:
By moving to vertical three-dimensional nanowire structures with gate-all-around configuration, the patent packs multiple nanowire channels vertically within a small footprint area. This vertical stacking approach dramatically increases device density without proportionally reducing lateral spacing requirements, as the channels are arranged in the vertical dimension rather than competing for lateral space.
Solution Approach 2:
The patent divides the channel into multiple discrete nanowire segments stacked vertically, with each nanowire forming an independent channel. This segmentation allows each nanowire to be independently controlled by the surrounding gate, enabling high density through vertical stacking while maintaining adequate spacing between individual nanowire channels for fabrication processes.
3Reliability
If conventional subfin isolation schemes are used to prevent source-to-drain leakage, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the complex subfin isolation scheme entirely by adopting nanowire structures with gate-all-around configuration. The complete gate wraparound provides inherent source-to-drain leakage prevention without requiring additional isolation structures or subfin doping processes, significantly simplifying the device architecture while maintaining reliability.
Solution Approach 2:
The gate-all-around structure serves multiple functions simultaneously: it provides channel control, prevents source-to-drain leakage, and eliminates the need for separate isolation schemes. This multi-functional approach replaces the complex multi-component isolation architecture with a unified gate structure that performs all necessary functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables higher-quality epitaxial source/drain growth, reduces leakage, and simplifies the integration process, resulting in higher-performing transistors with improved channel strain and reduced parasitic conduction paths.
Implementation Method 1
The semiconductor fin is then oxidized to form an insulator fin
Implementation Method 2
A pair of epitaxial source or drain structures is formed at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin
Data Source
AI summary
Gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator fin on an insulator substrate, are described. For example, an integrated circuit structure includes an insulator fin on an insulator substrate. A vertical arrangement of horizontal semiconductor nanowires is over the insulator fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal semiconductor nanowires, and the gate stack is overlying the insulator fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal semiconductor nanowires and at first and second ends of the insulator fin.