Gate-All-Around Nanowire Structure With Insulator Substrate Isolation
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Solution Overview
Problem
The challenge in integrated circuit fabrication lies in maintaining mobility improvement and short channel control as device dimensions scale below the 10 nanometer node, particularly in multi-gate transistors, where lithographic processes face constraints due to critical dimension and spacing trade-offs, and conventional bulk silicon substrates lead to undesired high leakage paths.
Innovation Solution
The implementation of gate-all-around integrated circuit structures with an insulator substrate, involving the removal of a semiconductor substrate and replacement with an insulator substrate, which includes forming a vertical arrangement of horizontal nanowires and a gate stack, and integrating epitaxial source or drain structures to enhance electrical isolation and reduce leakage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional bulk silicon substrates are used for multi-gate transistor fabrication, then manufacturing cost is reduced and fabrication process is simplified, but parasitic conduction paths increase leading to high leakage
Solution Approach 1:
The patent extracts and removes the bulk silicon substrate that causes parasitic conduction paths, replacing it with an insulator substrate. This eliminates the harmful parasitic conduction while maintaining the multi-gate transistor fabrication process
Solution Approach 2:
The patent changes the substrate parameter from conductive bulk silicon to insulating material, fundamentally altering the electrical properties of the substrate to block parasitic conduction paths while enabling proper electrical isolation of the transistor devices
2Quantity of substance
If device dimensions are scaled below 10 nanometer node, then device density is increased, but maintaining mobility improvement and short channel control becomes challenging
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanowire structures with gate-all-around configuration. This dimensional change provides superior electrostatic control and short channel effect suppression at sub-10nm nodes while enabling higher device density
Solution Approach 2:
The gate structure is nested around the nanowire channel in a gate-all-around configuration, providing three-dimensional electrostatic control. This nested arrangement ensures excellent short channel control and mobility improvement at scaled dimensions
3Quantity of substance
If lithographic processes are used to pattern fundamental building blocks at increased density, then device capacity is increased, but critical dimension and spacing constraints become overwhelming
Solution Approach 1:
The patent employs self-aligned fabrication processes where three-dimensional nanowire structures are formed before lithographic patterning. This dimensional approach relaxes lithographic constraints by enabling precise positioning through self-alignment rather than relying solely on lithographic critical dimensions
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the integration of nanowire/nanoribbon transistor architectures, reduces leakage, and enables robust transistor structures for low power applications by blocking parasitic conduction paths, thus improving device performance and layout efficiency.
Implementation Method 1
an insulator substrate, which includes forming a vertical arrangement of horizontal nanowires and a gate stack, and integrating epitaxial source or drain structures to enhance electrical isolation and reduce leakage
Data Source
AI summary
Gate-all-around integrated circuit structures having an insulator substrate, and methods of fabricating gate-all-around integrated circuit structures having an insulator substrate, are described. For example, an integrated circuit structure includes a semiconductor fin on an insulator substrate. A vertical arrangement of horizontal nanowires is over the semiconductor fin. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires, and the gate stack is overlying a channel region of the semiconductor fin. A pair of epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires and the semiconductor fin.