GAA Nanowire Gate Structure With High-k Sheaths for Threshold Control
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Solution Overview
Problem
The challenge in semiconductor device manufacturing is to achieve efficient scaling of n-type and p-type field effect transistors while maintaining device performance, as existing technologies face difficulties in forming gate-all-around (GAA) transistors with precise control over epitaxial layers and dielectric materials to optimize transistor performance.
Innovation Solution
The method involves forming an epitaxial stack with alternating SiGe and silicon layers, patterning fin elements, and using a gate-last process to create GAA transistors, where high-k dielectric sheaths and metal gate electrodes are formed to adjust work functions and reduce parasitic capacitance, allowing for single-layer metal gate electrodes and merged high-k dielectric sheaths around nanowires.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional CMOS scaling is used to reduce transistor size, then device density increases, but device performance deteriorates due to difficulty in forming gate-all-around structures with precise control
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional gate-all-around (GAA) nanowire structures. The gate electrode completely surrounds the nanowire channel in three dimensions, providing superior electrostatic control and enabling continued scaling while maintaining device performance. This dimensional change allows higher device density without the performance degradation encountered in traditional planar scaling.
Solution Approach 2:
The patent employs composite material structures including alternating layers of silicon and SiGe epitaxial layers forming the nanowire channel. The combination of different materials (silicon for channel, SiGe for strain engineering, high-k dielectrics for gate insulation, and metal gates for work function control) enables optimized device performance at scaled dimensions while achieving high device density.
2Manufacturing precision
If multiple metal layers are used in gate electrodes to adjust work functions, then transistor threshold voltage control improves, but device complexity increases
Solution Approach 1:
The patent applies local quality by forming different high-k dielectric sheath layers with different work functions at different locations around the nanowire. Specifically, a first high-k dielectric sheath with a first work function and a second high-k dielectric sheath with a second work function are deposited in sequence, allowing independent control of threshold voltages for n-type and p-type transistors sharing the same gate electrode structure, thereby achieving precise threshold voltage control without increasing structural complexity.
Solution Approach 2:
The gate electrode structure serves multiple functions simultaneously: it provides the gate field effect control, contains high-k dielectric sheaths for work function adjustment, and can accommodate different metal layers for fine-tuning threshold voltages. This multi-functional design enables precise threshold voltage control while maintaining a unified gate structure that reduces overall device complexity.
3Ease of manufacture
If conventional epitaxial layer formation is used, then manufacturing process is simple, but manufacturing precision deteriorates due to inability to form precise GAA transistor structures
Solution Approach 1:
The patent employs preliminary action by forming sacrificial nanowire structures and high-k dielectric sheaths before final gate electrode deposition. The high-k dielectric sheaths are deposited conformally on the nanowire surfaces prior to gate formation, ensuring precise positioning and thickness control. This preliminary structuring enables subsequent self-aligned processing steps that achieve high manufacturing precision for GAA structures while maintaining process simplicity through sequential deposition rather than complex lithography alignment.
Solution Approach 2:
The patent introduces high-k dielectric sheaths as intermediary layers between the nanowire channel and the gate electrode. These sheath layers serve as mediators that provide precise thickness control and work function adjustment, enabling accurate formation of the gate-all-around structure. The intermediary sheaths facilitate self-aligned processing and improve the precision of gate electrode positioning without requiring complex manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of GAA transistors with improved carrier mobility and reduced parasitic capacitance, allowing for various transistors with different threshold voltages and enhanced processing flexibility, thus addressing the scaling challenges in semiconductor device manufacturing.
Implementation Method 1
high-k dielectric sheaths and metal gate electrodes are formed to adjust work functions
Implementation Method 2
merged high-k dielectric sheaths around nanowires... reduced parasitic capacitance
Data Source
AI summary
A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.