GAA Transistor Oxide Barrier Layout for Lower Miller Capacitance
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Solution Overview
Problem
The use of hybrid fin structures in semiconductor devices increases space consumption, limits material selection for work-function metals, and reduces transistor performance by increasing Miller capacitance, prohibiting the formation of integrated circuitry like inverters in gate-all-around (GAA) transistors.
Innovation Solution
Incorporating an oxide-filled barrier structure between the nanosheet structures of PMOS and NMOS fin structures in semiconductor devices, which reduces distance, broadens the selection of work-function metals, and improves transistor performance by reducing Miller capacitance, enabling the formation of integrated circuitry such as inverters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If hybrid fin structures are used in GAA transistors, then device isolation is achieved, but space consumption increases and transistor performance decreases due to increased Miller capacitance
Solution Approach 1:
The patent segments the fin structure into PMOS fins and NMOS fins that are vertically stacked and laterally adjacent, allowing each fin type to be independently optimized while sharing common source/drain regions. This segmentation enables better performance compared to hybrid fin structures where PMOS and NMOS fins are interleaved in the same vertical stack.
Solution Approach 2:
The patent transitions from a lateral arrangement of PMOS and NMOS fins (hybrid fin) to a vertical stacking arrangement where PMOS fins and NMOS fins are stacked in the vertical dimension. This dimensional change reduces the lateral footprint and allows for better control of Miller capacitance while maintaining device isolation.
2Reliability
If hybrid fin structures are used, then device isolation is provided, but material selection for work-function metals is limited
Solution Approach 1:
By segmenting the device into separate PMOS fin regions and NMOS fin regions that are vertically stacked, the patent allows for independent work-function metal selection for each transistor type. Each fin can be equipped with appropriate metal materials (e.g., tungsten for PMOS, molybdenum for NMOS) without constraining the other, thereby broadening material selection versatility.
3Reliability
If hybrid fin structures are used, then device isolation is achieved, but integrated circuitry formation is prohibited
Solution Approach 1:
The patent segments PMOS and NMOS fins into separate vertical stacks that can be independently configured and connected. This segmentation allows for the formation of integrated circuitry such as inverters by selectively connecting the source/drain regions of different fin types, while maintaining device isolation through the vertical stacking architecture and insulator layers.
Data Source
AI summary
Some implementations described herein provide a semiconductor device having an oxide-filled barrier structure between structures of gate-all-around transistors included in the semiconductor device. The use of the oxide-filled barrier structure may reduce a distance separating nanosheet structures of a p-type metal-oxide semiconductor fin structure and an n-type metal-oxide semiconductor fin structure, broaden an availability of work-function metals for gate structures formed around nanochannels of the p-type metal-oxide semiconductor fin structure and n-type metal-oxide semiconductor structure, and improve a performance of the gate-all-around transistors by reducing miller capacitances of the gate-all-around transistors. Furthermore, the oxide-filled barrier structure may enable the combining of the p-type metal-oxide semiconductor fin structure and the n-type metal-oxide semiconductor fin structure to form a type of integrated circuitry, such as an inverter.