Mixed GAA Nanosheet, Nanowire, and Planar CMOS Layout for I/O
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Solution Overview
Problem
Vertically stacked gate-all-around (GAA) horizontal nanowire and nanosheet devices face limitations due to the restricted thickness of the gate dielectric layer, which is insufficient for applications requiring thicker dielectric layers, such as input/output (I/O) functions, limiting their suitability for certain circuit implementations.
Innovation Solution
The integration of GAA NW and GAA NS devices with planar devices on the same substrate, where GAA devices are placed in a core area for low-power and high-speed circuits, and planar devices are used in an I/O area for implementing I/O circuits, with GAA NS devices having wider channels for high-speed applications and GAA NW devices having narrower channels for low power consumption, allowing for flexible design integration and accommodating different circuit requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If vertically stacked GAA nanowire and nanosheet devices are used, then gate controllability and scalability are improved, but gate dielectric layer thickness is limited
Solution Approach 1:
The patent segments the semiconductor device into two distinct types: GAA devices for core logic functions and planar devices for I/O functions. This segmentation allows each device type to be optimized for its specific application, with planar devices providing the thick gate dielectric needed for I/O while GAA devices provide superior gate controllability for logic circuits.
Solution Approach 2:
The patent applies local quality by assigning different device architectures to different functional areas of the semiconductor device. GAA devices with their superior gate controllability are placed in the core area, while planar devices with thick gate dielectric are placed in the I/O area, allowing each region to have the properties needed for its specific function.
2Productivity
If GAA devices are used for all functions, then low-power and high-speed performance is achieved, but I/O functions requiring thick gate dielectric cannot be implemented
Solution Approach 1:
The patent creates a universal semiconductor device structure that can accommodate multiple device types and serve multiple functions. The same substrate supports both GAA devices for high-speed core logic and planar devices for I/O functions, making the device versatile enough to handle different circuit requirements within a single integrated structure.
Solution Approach 2:
The patent transitions from a single-device-type architecture to a multi-device-type architecture by adding the dimension of device architecture variety. Instead of using only vertically stacked GAA devices, the patent incorporates planar devices as well, allowing the system to meet diverse functional requirements including I/O applications that need thick gate dielectric.
3Length of stationary object
If planar devices are used for I/O functions, then thick gate dielectric can be achieved, but integration with GAA devices requires separate device regions
Solution Approach 1:
The patent merges previously separate device architectures (GAA and planar) into a single integrated semiconductor device. By combining both device types on the same substrate with shared source/drain regions and interconnect structures, the patent reduces overall device complexity despite the presence of multiple device types, achieving integration efficiency while maintaining the benefits of both architectures.
Data Source
AI summary
An integrated circuit includes a substrate, first and second n-type wells and a p-type well over the substrate, a first row of cells over the p-type well and the first n-type well, and a second row of cells over the p-type well and the second n-type well. The first and the second n-type wells sandwich the p-type well from a top view. The first row of cells include gate-all-around (GAA) nanosheet (NS) cells and GAA nanowire (NW) cells. The second row of cells include GAA NS cells and GAA NW cells. Each GAA NS cell includes an NMOS GAA NS transistor and a PMOS GAA NS transistor, each GAA NW cell includes an NMOS GAA NW transistor and a PMOS GAA NW transistor. Each transistor includes vertically stacked multiple first channels. The first channels of the GAA NS transistors are wider than the first channels of the GAA NW transistors.