3D Power Routing Layout for Scaled GAA Circuit Cells
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Solution Overview
Problem
As gate-all-around (GAA) transistors and circuit cells are scaled down, the VDD and VSS power routing consumes excessive routing resources, impacting cell scaling and performance.
Innovation Solution
Implementing a configuration with a single VSS line under the transistors and two VDD lines over and under the transistors, which improves cell performance and reduces routing complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional power routing is used with GAA transistors, then transistors can function properly, but routing resources are excessive and cell scaling is impacted
Solution Approach 1:
The patent transitions from planar power routing to three-dimensional routing by placing power lines on both the front side and back side of the circuit cell. This vertical utilization of space reduces the routing burden on the front side, enabling better cell scaling without increasing overall routing complexity
Solution Approach 2:
The power routing is segmented into multiple independent lines (first VDD line, second VDD line, VSS line) distributed across different layers and locations. This segmentation allows each line to be optimized independently and reduces the routing resource consumption of any single power line
2Reliability
If more routing resources are allocated to VDD and VSS power routing, then power delivery is improved, but cell area increases and scaling is reduced
Solution Approach 1:
By utilizing the back side of the circuit cell for power routing, the patent distributes power delivery paths across three-dimensional space rather than confining them to the front plane. This reduces the area consumed by power routing on the front side while maintaining reliable power delivery through multiple distributed paths
3Adaptability or versatility
If traditional power routing configurations are used, then manufacturing is straightforward, but routing complexity increases and scalability decreases
Solution Approach 1:
The patent resolves routing complexity by moving part of the power routing infrastructure to the back side, effectively trading increased three-dimensional routing complexity for reduced two-dimensional routing complexity on the front side, thereby improving scalability
Solution Approach 2:
Power routing is divided into multiple segmented lines across different layers, allowing each segment to be independently optimized and routed through the most efficient path, reducing overall routing complexity while maintaining scalability
Data Source
AI summary
A semiconductor device includes circuit cells, a VSS conductor, a first VDD conductor, and a second VDD conductor. Each of the circuit cells comprises at least one N-type transistor and at least one P-type transistor. The VSS conductor is under the circuit cells. The VSS conductor is electrically connected to source/drain features of the N-type transistors. The first VDD conductor is under the circuit cells. The first VDD conductor is electrically connected to source/drain features of the P-type transistors. The second VDD conductor is over the circuit cells. The second VDD conductor is electrically connected to the source/drain features of the P-type transistors and the first VDD conductor.