Gate-All-Around Semiconductor Structures With Recessed Bottom S/D Contacts
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Solution Overview
Problem
The integration of multi-gate devices in semiconductor manufacturing is challenging due to complexity and the need for improved gate control and reduced short-channel effects.
Innovation Solution
A semiconductor structure is formed with a gate-all-around transistor design, utilizing nanostructures surrounded by gate structures, and source/drain structures with enhanced contact areas through multiple patterning processes, including photolithography and self-aligned techniques, to reduce resistance and improve performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multi-gate devices are integrated to improve gate control and reduce short-channel effects, then device performance is improved, but fabrication complexity increases
Solution Approach 1:
The fabrication process is divided into multiple discrete patterning steps, including forming mandrels, depositing first spacers, removing mandrels, depositing second spacers, and selective removal. This segmentation allows complex multi-gate structures to be built through manageable sequential steps rather than attempting to form the complete structure in a single process
Solution Approach 2:
Mandrel structures are formed in advance as templates before the actual gate structures are created. These preliminary mandrels guide the subsequent spacer formation and material deposition processes, enabling precise positioning of the multi-gate structures before the mandrels are removed
2Productivity
If minimum feature size is scaled down to improve production efficiency and lower costs, then productivity is improved, but manufacturing complexity increases
Solution Approach 1:
The spacer structures self-align to the mandrels and previously formed features through conformal deposition processes. This self-aligned approach automatically positions features with precise spacing without requiring additional alignment steps, enabling scaled dimensions while maintaining manufacturing control
Solution Approach 2:
The patent uses vertical spacer deposition to define lateral feature positions and dimensions. By controlling spacer thickness in the vertical dimension through atomic layer deposition, precise lateral dimensions are achieved in the horizontal plane, enabling scalable feature sizes with controlled precision
3Reliability
If contact area between source/drain structures and contacts is increased to reduce resistance, then electrical conductivity is improved, but device area increases
Solution Approach 1:
The contact structures extend vertically through multiple spacer layers to achieve greater contact area with the source/drain regions. By utilizing the vertical dimension for contact extension rather than only lateral expansion, the patent increases contact area and reduces resistance without proportionally increasing the lateral device footprint
Data Source
AI summary
A method for forming the semiconductor device structure is provided. The method includes forming nanostructures over a substrate, and forming a first gate structure and a second gate structure wrapped around the nanostructures. The method includes forming a first source/drain (S/D) structure and a second S/D structure adjacent to the first gate structure, and the first S/D structure is between the first gate structure and the second gate structure. The method includes removing the first gate structure to form a first trench between the first S/D structure and the second S/D structure, and a sidewall of the first S/D structure and a sidewall of the second S/D structure are exposed by the first trench. The method includes forming a bottom S/D contact structure in the trench, and a bottom surface of the bottom S/D contact structure is lower than a bottommost surface of second gate structure.