GAA Transistor Sacrificial Layers for N/P Channel Optimization
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Solution Overview
Problem
As GAA transistors continue to scale, the use of sacrificial materials in their fabrication impacts performance differently for n-type and p-type devices, with disposable semiconductor interposers improving n-type performance but degrading p-type performance, and vice versa.
Innovation Solution
Implementing different sacrificial layers for n-type and p-type GAA transistors, such as silicon germanium layers for n-type and oxide layers for p-type, and employing specific masking and etching processes to form separate gate dielectrics for each type, optimizing performance by imparting stress or maintaining channel resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single type of sacrificial layer is used for both n-type and p-type devices, then manufacturing process is simplified, but device performance is compromised
Solution Approach 1:
The patent resolves the contradiction between manufacturing simplicity and device performance by implementing local quality through selective masking and etching processes. While the overall process remains relatively simple, targeted masking steps enable different sacrificial layer materials to be applied to different device types, optimizing performance without significantly complicating the manufacturing flow.
Solution Approach 2:
The patent applies segmentation by dividing the transistor fabrication process into separate treatment paths for n-type and p-type devices. The masking and etching processes are segmented to selectively remove sacrificial layers from specific device regions, allowing independent optimization of each device type while maintaining a unified manufacturing framework.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the performance of both n-type and p-type GAA transistors by tailoring the sacrificial materials and processing methods, improving channel resistance and overall device reliability.
Implementation Method 1
disposable semiconductor interposers improving n-type performance but degrading p-type performance
Implementation Method 2
oxide layers for p-type, and employing specific masking and etching processes to form separate gate dielectrics for each type, optimizing performance by imparting stress or maintaining channel resistance
Data Source
AI summary
Methods of fabricating different type multigate transistors using different sacrificial layers, such as dummy semiconductor interposers (DSI) for n-type multigate transistors and dummy oxide interposers (DOI) for p-type multigate transistors, are disclosed herein. An exemplary method includes masking an n-type transistor region when forming DOIs in a p-type transistor region and gaps for inner spacers in the p-type transistor region (e.g., formed by recessing the DOIs), masking the p-type transistor region when forming gaps for inner spacers in the n-type transistor region (e.g., formed by recessing the DSIs), and forming the inner spacers in the gaps in the p-type transistor region and the gaps in the n-type transistor region simultaneously or separately. The method may include, during a gate replacement process, masking the n-type transistor region when removing the DOIs in the p-type transistor region and masking the p-type transistor region when removing the DSIs in the n-type transistor region.