GAA Transistor S/D Isolation Structure for Leakage Suppression
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Solution Overview
Problem
In the fabrication of gate-all-around (GAA) transistors, conventional methods result in strong leakage current due to the gate structure engaging the top surface of the semiconductor substrate under the stacked channel structures.
Innovation Solution
The introduction of an insulating feature interposing the source/drain features and the semiconductor structures underneath, which suppresses leakage current by creating a barrier between the gate and the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a gate structure extending around the bottommost channel structure is formed in conventional GAA process, then gate control is improved and access to the channel on multiple sides is achieved, but strong leakage current occurs under the stacked channel structures due to engagement with the top surface of the semiconductor substrate
Solution Approach 1:
An insulating dielectric layer is introduced as an intermediary between the gate structure and the semiconductor substrate. This dielectric layer is deposited to cover the top surface of the substrate and extend into the trench, positioning itself between the gate structure and substrate to block the leakage current path while allowing the gate structure to maintain its wrap-around configuration for improved gate control
Solution Approach 2:
The gate structure is segmented into distinct portions: a first portion that contacts the channel structure for control functionality, and a second portion that is electrically isolated from the substrate by the insulating dielectric layer. This segmentation allows the gate to perform its control function while preventing the harmful leakage current path
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.