GAA Seal Ring Structure to Prevent Channel Release
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing seal ring structures in semiconductor technology are inadequate for protecting gate-all-around devices such as nanosheet devices, particularly during fabrication processes.
Innovation Solution
The development of a seal ring structure that includes stacked semiconductor layers and sacrificial gate structures, with the poly gates removed and the semiconductor layers in the seal ring preserved to prevent channel release, allowing for the formation of high-k metal gates and subsequent BEOL processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If existing seal ring structures are used, then general protection is provided, but protection against moisture degradation and ionic contamination is insufficient for gate-all-around devices
Solution Approach 1:
The seal ring structure is differentiated into two regions: a first region with a first semiconductor layer and a second region with a second semiconductor layer having different etch selectivity. This local quality variation enables the seal ring to provide enhanced protection for gate-all-around devices while maintaining compatibility with fabrication processes through selective etching behavior in different regions.
Solution Approach 2:
The seal ring employs composite semiconductor layer structures with different materials or compositions in the first and second regions. These composite layers exhibit different etch selectivities, allowing the seal ring to simultaneously provide robust protection and process compatibility during gate-all-around device fabrication.
2Reliability
If conventional seal ring fabrication is used, then simple structure is maintained, but channel release occurs compromising device protection
Solution Approach 1:
The seal ring is segmented into multiple semiconductor layers (first semiconductor layer and second semiconductor layer) with distinct etch selectivities. This segmentation prevents channel release by creating a structured barrier that maintains integrity during fabrication processes, while the layered composition remains manageable within existing manufacturing capabilities.
Solution Approach 2:
The invention changes the etch selectivity parameter between different semiconductor layers in the seal ring. By controlling the etch selectivity differences between the first and second semiconductor layers, the structure prevents channel release during fabrication without requiring overly complex manufacturing procedures.
3Reliability
If additional semiconductor layers are added to seal ring, then protection is enhanced, but manufacturing complexity increases
Solution Approach 1:
The seal ring incorporates semiconductor layers with locally differentiated properties, where the first and second semiconductor layers have different etch selectivities. This local quality approach enhances seal ring stability and robustness while maintaining ease of manufacture by utilizing standard semiconductor fabrication techniques that can handle multi-layer structures with different material properties.
Data Source
AI summary
A semiconductor structure includes a substrate, a circuit region, and a seal ring surrounding the circuit region. The circuit region includes two first source/drains, first semiconductor layers connecting the two first source/drains, and a first gate disposed between the two first source/drains and wrapping around each of the first semiconductor layers. The seal ring includes two epitaxially grown semiconductor structures, second semiconductor layers, third semiconductor layers, and a second gate. The second and the third semiconductor layers are alternately stacked one over another to form a stack of layers. A topmost layer of the stack is one of the third semiconductor layers. The second gate is disposed between the two epitaxially grown semiconductor structures and above the topmost layer of the stack. The first and the third semiconductor layers include a first semiconductor material. The second semiconductor layers include a second semiconductor material different from the first semiconductor material.